2020 32nd International Conference on Microelectronics (ICM)最新文献_第4页

Fractional-Order Image Segmentation for Security Surveillance 用于安全监控的分数阶图像分割

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331787

Samar M. Ismail

引用次数: 1

ICM 2020 Program ICM 2020计划

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/icm50269.2020.9331774

引用次数: 0

Low-Cost FMCW Radar Human-Vehicle Classification Based on Transfer Learning 基于迁移学习的低成本FMCW雷达人车分类

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331808

Ali Rizik, A. Randazzo, R. Vio, A. Delucchi, H. Chible, D. Caviglia

引用次数: 1

Analysis and Synthesis of Respiratory Rate for Female Patients 女性患者呼吸频率的分析与综合

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331782

Edder Sebastian Mendoza Garibay, M. S. Ullah

引用次数: 0

On Series Connections of Fractional-Order Elements and Memristive Elements 分数阶元与忆元的级数连接

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331507

Nariman A. Khalil, M. Fouda, L. Said, A. Radwan, A. Soliman

引用次数: 1

New Proposed Methodology for Radiation Hardening By Design of MOS Circuits 通过设计 MOS 电路实现辐射加固的新方法建议

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331495

H. H. Shaker, A. Saleh, M. R. Amin, S. Habib

引用次数: 0

Detecting Botnet Attacks in IoT Environments: An Optimized Machine Learning Approach 检测物联网环境中的僵尸网络攻击:一种优化的机器学习方法

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331794

M. Injadat, Abdallah Moubayed, A. Shami

{"title":"Detecting Botnet Attacks in IoT Environments: An Optimized Machine Learning Approach","authors":"M. Injadat, Abdallah Moubayed, A. Shami","doi":"10.1109/ICM50269.2020.9331794","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331794","url":null,"abstract":"The increased reliance on the Internet and the corresponding surge in connectivity demand has led to a significant growth in Internet-of-Things (IoT) devices. The continued deployment of IoT devices has in turn led to an increase in network attacks due to the larger number of potential attack surfaces as illustrated by the recent reports that IoT malware attacks increased by 215.7% from 10.3 million in 2017 to 32.7 million in 2018. This illustrates the increased vulnerability and susceptibility of IoT devices and networks. Therefore, there is a need for proper effective and efficient attack detection and mitigation techniques in such environments. Machine learning (ML) has emerged as one potential solution due to the abundance of data generated and available for IoT devices and networks. Hence, they have significant potential to be adopted for intrusion detection for IoT environments. To that end, this paper proposes an optimized ML-based framework consisting of a combination of Bayesian optimization Gaussian Process (BO-GP) algorithm and decision tree (DT) classification model to detect attacks on IoT devices in an effective and efficient manner. The performance of the proposed framework is evaluated using the Bot-IoT-2018 dataset. Experimental results show that the proposed optimized framework has a high detection accuracy, precision, recall, and F-score, highlighting its effectiveness and robustness for the detection of botnet attacks in IoT environments.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126377065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

An Energy-Efficient Temperature Sensor Using CMOS Thyristor Delay Elements 采用CMOS晶闸管延迟元件的高能效温度传感器

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331790

Ian Christian Fernandez, M. T. D. Leon, A. Alvarez, M. Rosales

引用次数: 2

Design of Multiplicative Inverse Value Generator using Logarithm Method for AES Algorithm 基于对数法的AES算法乘法逆值发生器设计

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331497

Goh Yie Yen, S. Z. M. Naziri, R. C. Ismail, M. I. N. Isa, R. Hussin

{"title":"Design of Multiplicative Inverse Value Generator using Logarithm Method for AES Algorithm","authors":"Goh Yie Yen, S. Z. M. Naziri, R. C. Ismail, M. I. N. Isa, R. Hussin","doi":"10.1109/ICM50269.2020.9331497","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331497","url":null,"abstract":"Advanced Encryption Standard (AES) algorithm is one of the most widely used symmetric block cipher that is utilized in data protection through symmetric cryptography algorithm, as it offers high efficiency and ability in securing information. In AES, the SubByte/InvSubByte transformation costs an amount of memories for the lookup tables (LUT) that leads to area usage in hardware. As per mathematical equations, the SubByte/InvSubByte is able to share the same resource which is the multiplicative inverse value table. Instead of using LUTs, the multiplicative inverse values can be generated on-the-fly as needed. Therefore, this paper presents the custom hardware design and implementation of multiplicative inverse value generator using logarithm method specifically for AES algorithm. The logarithm method benefits the usage of antilog and log values in obtaining the multiplicative inverse value. The EDA tools as Intel Quartus Prime, Synopsys Design Compiler and IC Compiler are used to perform functional simulation, on synthesis analysis and block-level implementation. Detailed comparison is made between this work and previous implementation. The newly designed multiplicative inverse value generator has achieved the improvement on speed and area as compared to previous implementation. The area of the design is reduced around 8.5% with current improvement of 63.091 μm2, while the speed has increased to 2.54 ns with a positive slack of 0.11 ns, which is shorter than the previous implementation. The new design also outreached the performance of the common LUT-based design.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123132185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA Implementation of Interval Type-2 Fuzzy System Based on Nie-Tan Algorithm 基于Nie-Tan算法的区间2型模糊系统的FPGA实现

2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331498

R. Maciel, R. Moreno, T. Pimenta, P. Rizol

{"title":"FPGA Implementation of Interval Type-2 Fuzzy System Based on Nie-Tan Algorithm","authors":"R. Maciel, R. Moreno, T. Pimenta, P. Rizol","doi":"10.1109/ICM50269.2020.9331498","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331498","url":null,"abstract":"The Interval Type-2 Fuzzy Logic Systems – IT2FLS processors have been widely used in control processes that analyzes uncertain information. The IT2FLS presents a superior performance compared to other methods for high uncertainty applications. In real-time control applications, circuit parallelism strategies increase the number of Fuzzy Logic Inference Per Second (FLIPS). This technique demands more hardware resources compared to sequential processing, which can make it difficult to use platforms that have resource limitations. This article presents an IT2FLS architecture implementation minimizes the use of parallel processing in the implementation in the inference engine and maintains the amount of FLIPS suitable for real-time applications. The proposed IT2FLS architecture is implemented in FPGA. It uses the type reduction circuits based on Nie-Tan algorithm. The hardware consists of two 8-bit inputs with four Gaussian membership functions for each one, sixteen rules and an 8-bit output with seven membership functions. The results of the FPGA implementation are compared with the same architecture implemented in Matlab® using the Toolbox for type-2 fuzzy.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128040758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0