FPGA Implementation of Interval Type-2 Fuzzy System Based on Nie-Tan Algorithm

Abstract

The Interval Type-2 Fuzzy Logic Systems – IT2FLS processors have been widely used in control processes that analyzes uncertain information. The IT2FLS presents a superior performance compared to other methods for high uncertainty applications. In real-time control applications, circuit parallelism strategies increase the number of Fuzzy Logic Inference Per Second (FLIPS). This technique demands more hardware resources compared to sequential processing, which can make it difficult to use platforms that have resource limitations. This article presents an IT2FLS architecture implementation minimizes the use of parallel processing in the implementation in the inference engine and maintains the amount of FLIPS suitable for real-time applications. The proposed IT2FLS architecture is implemented in FPGA. It uses the type reduction circuits based on Nie-Tan algorithm. The hardware consists of two 8-bit inputs with four Gaussian membership functions for each one, sixteen rules and an 8-bit output with seven membership functions. The results of the FPGA implementation are compared with the same architecture implemented in Matlab® using the Toolbox for type-2 fuzzy.