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2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)最新文献

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A Wireless Power Design with High PCE and Fast Transient Response over a Large Loading Range for Multi-channel Neural Stimulators 多通道神经刺激器大负载范围内高PCE、快速瞬态响应的无线电源设计
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090269
Weisong Liang, Xu Liu, Weijian Chen, Ze-Xi Lu, Peiyuan Wan, Zhijie Chen
{"title":"A Wireless Power Design with High PCE and Fast Transient Response over a Large Loading Range for Multi-channel Neural Stimulators","authors":"Weisong Liang, Xu Liu, Weijian Chen, Ze-Xi Lu, Peiyuan Wan, Zhijie Chen","doi":"10.1109/APCCAS55924.2022.10090269","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090269","url":null,"abstract":"Brain-machine interface(BMI) with implantable bioelectronics systems can provide an alternative way to cure neural diseases, while a wireless power transfer (WPT) system plays an important role in providing a stable voltage supply for the implanted chip. A WPT for multichannel neural stimulators with high power conversion efficiency(PCE) and low power dissipation over a large loading range is proposed in this work. Both the internal Vth cancelation (IVC) and the dynamic bulk modulation (DBM) schemes are used to maximize the PCE of rectifiers. Besides, a reverse nested miller compensation (RNMC) LDO with a transient enhancer is proposed for the WPT system. Simulation results show that the total PCE is 55% at its peak, and the power consumption is 0.55 mW and 22.5 mW at standby (SB) and full stimulation (ST) load, respectively. For a full load transition, the overshoot and downshoot of the LDO are 110mV and 71 mV, respectively, which help improve the load transient response during neural stimulation.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123634735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Matrix Filter Using Discrete Cosine Transform and Path Graph 基于离散余弦变换和路径图的矩阵滤波器设计
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090257
C. Tseng, Su-Ling Lee
{"title":"Design of Matrix Filter Using Discrete Cosine Transform and Path Graph","authors":"C. Tseng, Su-Ling Lee","doi":"10.1109/APCCAS55924.2022.10090257","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090257","url":null,"abstract":"In this paper, the design of matrix filter using discrete cosine transform (DCT) and path graph is presented. First, the DCT is used to design matrix filter without considering the prior information of transform basis of DCT. Then, the graph spectral theory is employed to show that the DCT is the graph Fourier transform (GFT) of path graph such that graph filter method can be used to design and implement the matrix filter. Next, the weighted least squares (WLS) method is applied to design the graph filters which can be used to implement the matrix filter with low computational complexity because graph shift matrix is very sparse. Finally, the design examples of matrix Butterworth filter and matrix Riesz fractional order differentiator (FOD) are illustrated to demonstrate the effectiveness of the proposed matrix filter design method.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128447711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Fast-Transient Response Capacitor-Less FVF-LDO in 22-nm CMOS Technology 基于22纳米CMOS技术的快速瞬态响应无电容FVF-LDO
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090387
Ruolin Zhou, Heng Liu, Wending Qi, Xian Tang, Songping Mai
{"title":"A Fast-Transient Response Capacitor-Less FVF-LDO in 22-nm CMOS Technology","authors":"Ruolin Zhou, Heng Liu, Wending Qi, Xian Tang, Songping Mai","doi":"10.1109/APCCAS55924.2022.10090387","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090387","url":null,"abstract":"This paper presents a capacitor-less low-dropout regulator(LDO) based on flipped voltage follower(FVF) structure to achieve fast-transient response and small voltage spikes with a high power-supply ripple rejection (PSRR) performance. This capacitor-less LDO, implemented in 22 nm CMOS technology, is designed for the Internet-of-Things(IoT) application. With a method of adaptive biasing, this LDO can reduce quiescent by tracking load variations and improve the load transient response by tracing the variation of output voltage. Experimental results show that the maximal overshoot and undershoot with adaptive biasing circuit are about 25.06 mV and 38.73 mV, respectively, at the load current toggling between 100 uA and 10 mA with edge time of 300 ns. At the same time, its PSRR can achieve about -60.7 dB at 100 kHz and -41.2 dB at 1 MHz with quiescent current of 11 uA.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130712899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Vector Pair Based DWA Algorithm for Linearity Enhancement of CDACs in the NS-SAR ADC NS-SAR ADC中基于矢量对的DWA线性增强算法
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090367
Xiao Han, Xiyuan Tang, Yanxing Suo, Qiao Cai, Xinzi Xu, T. Wan, Yang Zhao
{"title":"A Vector Pair Based DWA Algorithm for Linearity Enhancement of CDACs in the NS-SAR ADC","authors":"Xiao Han, Xiyuan Tang, Yanxing Suo, Qiao Cai, Xinzi Xu, T. Wan, Yang Zhao","doi":"10.1109/APCCAS55924.2022.10090367","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090367","url":null,"abstract":"The conventional DWA algorithm is not direct to be used for the mismatch shaping of the SAR-type DACs that are widely used in NS-SAR ADCs. The emerging DWA algorithm requires an extra coarse ADC which complicates the system and thus limits the figure of merit of the high-resolution NS-SAR ADC. This paper presents vector pair based DWA algorithm omitting the necessity of the coarse ADC. Employing two vectors that initiate at adjacent positions and respectively update to circularly select the elements in a reversed direction, then the mismatch error of the SAR-type DAC is first-order shaped. Not only the theoretical proof is given but also the shaping performance is simulated in this paper.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"31 5-6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114135994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE 一种具有小型化正交混合电路的60 ghz CMOS平衡功率放大器，输出功率为19.0 dbm，峰值PAE为24.4%
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090372
Zhi-Li Zhang, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma
{"title":"A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE","authors":"Zhi-Li Zhang, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma","doi":"10.1109/APCCAS55924.2022.10090372","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090372","url":null,"abstract":"In this paper, a 60-GHz CMOS balanced power amplifier (PA) is proposed. Two miniaturized quadrature hybrids are utilized to realize power splitting and power combining. The compact hybrids can achieve good input and output matching performances. Transistor-layout optimization is taken into consideration to boost the output power and improve the power-added efficiency (PAE). The balanced PA is designed in 65-nm bulk CMOS and all the electromagnetic (EM) simulations of passive devices are executed in the EM tool. Post-layout simulation results show that the proposed balanced PA realizes a small-signal gain of 29.1 dB at 60 GHz with an 11-GHz bandwidth. With a 1.2-V supply voltage and 300-mW power consumption, the balanced PA achieves a saturated output power of 19.0 dBm and 24.4% peak PAE at 60 GHz, which is suitable for 60-GHz wireless systems.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114078505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators 基于22nm FDSOI 8T SRAM的高效DNN加速器时域CIM
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090315
Yongliang Zhou, Zuo Cheng, Han Liu, Tianzhu Xiong, Bo Wang
{"title":"A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators","authors":"Yongliang Zhou, Zuo Cheng, Han Liu, Tianzhu Xiong, Bo Wang","doi":"10.1109/APCCAS55924.2022.10090315","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090315","url":null,"abstract":"In memory computation for Deep neural networks (DNNs) applications is an attractive approach to improve the energy efficiency of MAC operations under a memory-wall constraint, since it is highly parallel and can save a great amount of computation and memory access power. In this paper, we propose a time-domain compute in memory (CIM) design based on Fully Depleted Silicon On Insulator (FD-SOI) 8T SRAM. A $128mathrm{x}128$ 8T SRAM bit-cell array is built for processing a vector-matrix multiplication (or parallel dot-products) with $8mathrm{x}$ binary (0 or 1) inputs, in-array 8-bits weights, and 8bits output precision for DNN applications. The column-wise TDC converts the delay accumulation results to 8bits output codes using replica bit-cells for each conversion. Monte-Carlo simulations have verified both linearity and process variation. The energy efficiency of the 8bits operation is 32.8TOPS/W at 8bits TDC mode using 0.9V supply and 20MHz.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"406 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122926524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Accurate and Time-Efficient Subtractor by Cross Format Coding in Stochastic Computing 随机计算中一种精确、省时的交叉格式编码减法
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090251
Zhihuai Zhang, Weiqian Zhang, S. Xiong, Yudi Zhao
{"title":"An Accurate and Time-Efficient Subtractor by Cross Format Coding in Stochastic Computing","authors":"Zhihuai Zhang, Weiqian Zhang, S. Xiong, Yudi Zhao","doi":"10.1109/APCCAS55924.2022.10090251","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090251","url":null,"abstract":"Different from binary computation, stochastic computation (SC), as a new paradigm, uses stochastic bit stream (SBS) to encode data. By simplifying computing elements, the circuit area can be greatly reduced. SBS can be generated by a stochastic number generator (SNG) with a variety of formats. In this work, we use unipolar (UP) and bipolar (BP) formats to optimize the traditional SC subtractor, which is named the UP-to-BP Subtractor (UBS). A new cross format coding (CFC) method is proposed for stochastic computing, which combines the UP and BP format, and is applied to Sobel edge detection in image processing algorithms. The fault tolerance and detection efficacy of the proposed CFC method and conventional binary computing are compared in this paper. By using the CFC method, the detected F-Score is improved by 0.15(23%). If the F-score remains unchanged, the processing speed can be about 10 times faster.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129298157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Logic Locking for Hardware Security Using Voltage-Gated Spin-orbit Torque Magnetic Tunnel Junction 基于电压门控自旋轨道转矩磁隧道结的硬件安全逻辑锁定
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090297
Divyanshu Divyanshu, R. Kumar, Danial Khan, S. Amara, Y. Massoud
{"title":"Logic Locking for Hardware Security Using Voltage-Gated Spin-orbit Torque Magnetic Tunnel Junction","authors":"Divyanshu Divyanshu, R. Kumar, Danial Khan, S. Amara, Y. Massoud","doi":"10.1109/APCCAS55924.2022.10090297","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090297","url":null,"abstract":"With the rapid interest in exploiting the advantages of beyond CMOS devices in various applications, we explore, in this work, voltage-gated spin-orbit torque-assisted magnetic tunnel junction (VGSOT-MTJ) based on the Verilog-A behavioral model to design a possible logic locking system for hardware security. The VGSOT MTJ can switch without needing a magnetic field, and the antiferromagnetic (AFM) strip provides SOT and an exchange bias, thus paving the way for more practical applications. Compared to spin transfer torque (STT) MTJs, these AFM-based SOT-MTJs do not require passing high write current through the thin layer of the MTJ stack, thus increasing their endurance significantly. Compared with Heavy metal (HM) based SOT-MTJ, the VGSOT-MTJ utilizes the voltage-controlled magnetic anisotropy (VCMA) effect to significantly reduce the $J_{mathbf{SOT},mathbf{critical}}$. We perform a Monte-Carlo analysis to account for the effect of Process Variation on critical MTJ parameters for designing the logic locking block. Eye Diagram test, transient performance, and the effect of thermal noise are analyzed for High-Speed Integrated Circuits systems, and the results are compared with HM-based SOT-assisted MTJ as both are three-terminal (3T) MTJ structures.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116103670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
IEEE APCCAS 2022
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/apccas55924.2022.10090265
{"title":"IEEE APCCAS 2022","authors":"","doi":"10.1109/apccas55924.2022.10090265","DOIUrl":"https://doi.org/10.1109/apccas55924.2022.10090265","url":null,"abstract":"","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116389196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Subpixel Interpolation Disparity Refinement for Semi-Global Matching 半全局匹配的亚像素插值视差细化
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Pub Date : 2022-11-11 DOI: 10.1109/APCCAS55924.2022.10090384
Yunhao Ma, Xiwei Fang, Pingcheng Dong, Xinyu Guan, Kebo Li, Lei Chen, F. An
{"title":"Subpixel Interpolation Disparity Refinement for Semi-Global Matching","authors":"Yunhao Ma, Xiwei Fang, Pingcheng Dong, Xinyu Guan, Kebo Li, Lei Chen, F. An","doi":"10.1109/APCCAS55924.2022.10090384","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090384","url":null,"abstract":"Semi-Global Matching (SGM) algorithms and their corresponding hardware accelerators, which focus on stereo matching, have been developed in the last few years. However, the interpolation for disparity is much indispensable for real-world applications but still remains refining. This work presents a pixel-level pipeline architecture for the disparity refinement for SGM in case of computing disparity, which refines disparity through subpixel interpolation with an optimized cosine look up table and a compute-friendly parallel divider. The hardware architecture based on optimization algorithms has reached a error rate of only 6.33% for tradition background and 7.30% for occlusion condition, achieved in real-time FPGA as well.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117063799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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