Yunhao Ma, Xiwei Fang, Pingcheng Dong, Xinyu Guan, Kebo Li, Lei Chen, F. An
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引用次数: 0
Abstract
Semi-Global Matching (SGM) algorithms and their corresponding hardware accelerators, which focus on stereo matching, have been developed in the last few years. However, the interpolation for disparity is much indispensable for real-world applications but still remains refining. This work presents a pixel-level pipeline architecture for the disparity refinement for SGM in case of computing disparity, which refines disparity through subpixel interpolation with an optimized cosine look up table and a compute-friendly parallel divider. The hardware architecture based on optimization algorithms has reached a error rate of only 6.33% for tradition background and 7.30% for occlusion condition, achieved in real-time FPGA as well.