{"title":"IOLTS 2018 Committees","authors":"","doi":"10.1109/iolts.2018.8474123","DOIUrl":"https://doi.org/10.1109/iolts.2018.8474123","url":null,"abstract":"","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130478613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis","authors":"Kento Hasegawa, M. Yanagisawa, N. Togawa","doi":"10.1109/IOLTS.2018.8474113","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474113","url":null,"abstract":"Microcontrollers are widely used in electric devices such as smart phones, televisions, and other smart IoT (Internet-of-Things) devices. Because of the increase of these smart IoT devices, the security of hardware devices becomes a serious concern. In this paper, we propose a method which detects the existence of malfunctions implemented in microcontrollers utilizing power analysis. Our method firstly measures power consumption of the target device and classifies its waveform into the sleep-mode part, in which a microcontroller saves power, and the active-mode part, in which a microcontroller works in a normal operation. After that, we focus on the active-mode part and extract several features from the waveform, which effectively distinguish between normal operations and malfunctions. Finally, we classify the features and identify whether malfunctions exist or not. Our experimental results demonstrate that our proposed method successfully detects the existence of malfunctions in our benchmark.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130004716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Marcello Traiola, A. Savino, M. Barbareschi, S. Carlo, A. Bosio
{"title":"Predicting the Impact of Functional Approximation: from Component- to Application-Level","authors":"Marcello Traiola, A. Savino, M. Barbareschi, S. Carlo, A. Bosio","doi":"10.1109/IOLTS.2018.8474072","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474072","url":null,"abstract":"Approximate Computing (AxC) trades off between the level of accuracy required by the user and the actual precision provided by the computing system to achieve several optimizations such as performance improvement, energy and area reduction etc. Several AxCtechniques have been proposed so far in the literature. They work at different abstraction levels and propose both hardware and software implementations. The common issue of all existing approaches is the lack of a methodology to estimate the impact of a given AxC technique on the application-level accuracy. In this paper we propose a probabilistic approach to predict the relation between component-level functional approximation and application-level accuracy. Experimental results on a set of benchmark applications show that the proposed approach is able to estimate the approximation error with good accuracy and very low computation time.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125207041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Honorio Martín, L. Entrena, Sophie Dupuis, G. D. Natale
{"title":"A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation","authors":"Honorio Martín, L. Entrena, Sophie Dupuis, G. D. Natale","doi":"10.1109/IOLTS.2018.8474077","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474077","url":null,"abstract":"Hardware Trojans have become in the last decade a major threat in the Integrated Circuit industry. Many techniques have been proposed in the literature aiming at detecting such malicious modifications in fabricated ICs. For the most critical circuits, prevention methods are also of interest. The goal of such methods is to prevent the insertion of a Hardware Trojan thanks to ad-hoc design rules. In this paper, we present a novel prevention technique based on approximation. An approximate logic circuit is a circuit that performs a possibly different but closely related logic function, so that it can be used for error detection or error masking where it overlaps with the original circuit. We will show how this technique can successfully detect the presence of Hardware Trojans, with a solution that has a smaller impact than triplication.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134075120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"AMS-RF test quality: Assessing defect severity.","authors":"Valentin Guiterrez, A. Ginés, G. Léger","doi":"10.1109/IOLTS.2018.8474109","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474109","url":null,"abstract":"In safety critical applications there is a demand for estimating defect coverage in order to meet stringent quality levels. However, defect simulation of complex AMS-RF circuits is computationally expensive since achieving good confidence interval requires sampling many defects. In this paper, we show on a practical case of study that it may be beneficial to complement defect coverage with fault coverage and assess the severity of defect escapes to get a complete picture of test quality.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124501032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Helen-Maria Dounavi, Yiorgos Sfikas, Y. Tsiatouhas
{"title":"Periodic Aging Monitoring in SRAM Sense Amplifiers","authors":"Helen-Maria Dounavi, Yiorgos Sfikas, Y. Tsiatouhas","doi":"10.1109/IOLTS.2018.8474169","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474169","url":null,"abstract":"In nanometer technologies the reliability of Static Random Access Memories (SRAMs) is seriously affected by transistor Bias-Temperature Instability (BTI). In this work, a circuit for the periodic aging monitoring in SRAM sense amplifiers (due to BTI related transistor degradation) is presented. This degradation increases the input offset voltage of a sense amplifier. Periodic monitoring provides the ability to avoid SRAM failures by detecting over aged sense amplifiers (near failure) and then properly react in order to maintain the memory reliable operation. The monitoring scheme is based on a low cost differential ring oscillator, which can be easily embedded in an SRAM array without affecting the normal mode of operation.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122056532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Real-Time Validation of Fault-Tolerant Mixed-Criticality Systems","authors":"Stefano Esposito, J. Sini, M. Violante","doi":"10.1109/IOLTS.2018.8474091","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474091","url":null,"abstract":"Modern avionics and space applications are characterized by increasing performance requirements. To satisfy such requirements, the use of commercial-off-the-shelf (COTS) multi-processor system-on-chips (MPSoCs) is a convenient solution. However, such systems are not developed for the avionic use case, therefore a validation approach is in order. In this paper, a validation approach is proposed for fault isolation, detection, and recovery mechanisms applied to mitigate fault effects in mixed-criticality systems. The approach is based on a combination of hardware-in-the-loop testing and fault injection techniques. Experimental results prove that the proposed approach does not interfere with the temporal behavior of the system under-test while allowing a realistic test of the software.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131590579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"To Detect or to Correct?","authors":"A. Bramnik, Yiannakis Sazeides","doi":"10.1109/IOLTS.2018.8474073","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474073","url":null,"abstract":"This paper reviews state of art techniques used to protect memory arrays in processors against errors. We discuss the strength and weakness of various techniques and explain how to lessen some of their limitations. We also perform a comparative analysis of the various techniques in the presence of multi cell upsets. This study reveals that there are situations where a less costly only detection code may be advantageous over a more expensive code that can detect and correct errors. This indicates that correction vs detection trade-offs need to be revisited in the presence of multi cell upsets.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123723721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shervin Roshanisefat, Harshith K. Thirumala, K. Gaj, H. Homayoun, Avesta Sasan
{"title":"Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes","authors":"Shervin Roshanisefat, Harshith K. Thirumala, K. Gaj, H. Homayoun, Avesta Sasan","doi":"10.1109/IOLTS.2018.8474189","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474189","url":null,"abstract":"In this paper, we investigate the strength of six different SAT solvers in attacking various obfuscation schemes. Our investigation revealed that Glucose and Lingeling SAT solvers are generally suited for attacking small-to-midsize obfuscated circuits, while the MapleGlucose, if the system is not memory bound, is best suited for attacking mid-to-difficult obfuscation methods. Our experimental result indicates that when dealing with extremely large circuits and very difficult oufuscation problems, the SAT solver may be memory bound, and Lingeling, for having the most memory efficient implementation, is the best suited solver for such problems. Additionally, our investigation revealed that SAT solver execution times may vary widely across different SAT solvers. Hence, when testing the hardness of an obfuscation methods, although the increase in difficulty could be verified by one SAT solver, the pace of increase in difficulty is dependent on the choice of a SAT solver.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126536653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}