2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)最新文献

{"title":"Self-Healing Imager Based on Detection and Conciliation of Defective Pixels","authors":"Ghislain Takam Tchendjou, E. Simeu","doi":"10.1109/IOLTS.2018.8474149","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474149","url":null,"abstract":"This paper presents imager self-healing method based on detection and correction of defective pixels in the produced image file. The proposed method uses a neighborhood analysis with simple arithmetic operations including distance between the to-be-tested pixel and its neighbor pixels. A 2-dimensional 3 by 3 gray-scale image matrix around the to-be-tested pixel is used to estimate an expected pixel value and a weighted average. This average value is used as an adaptive threshold of the difference value between expected and actual pixel values. The performances in terms of sensibility, specificity, predictive values, and phi-coefficient of the produced results on a set of 144 distorted images (24 references images $times$ 6 distortion types), are compared to another dead pixel detection methods performances. Experimental results demonstrated that our proposal produces the best results.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114292932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits","authors":"Ryota Ishikawa, Masashi Tawada, M. Yanagisawa, N. Togawa","doi":"10.1109/IOLTS.2018.8474263","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474263","url":null,"abstract":"Due to the continuous demand of small-sized cir- cuits in the fields of image processing and artificial intelligence, stochastic computing has attracted much attention. In stochastic computing, stochastic numbers composed of randomly generated bit streams are used for computation. When inputting two or more identical values to a stochastic circuit, their arithmetic operation results can be inaccurate. In this paper, a stochastic number duplicator called $RRR$ (Register based Re-arrangement circuit using a Random bit stream) duplicator is introduced and is evaluated by applying to composite arithmetic circuits including re-convergence paths. The stochastic numbers duplicated by $RRR$ duplicator have the equivalent values to its input stochastic numbers but have independent bit streams, effectively utilizing bit re-arrangement based on randomized bit streams. It is applied to composite arithmetic circuits and its accuracy and area/delay requirements are evaluated. The results demonstrate that $RRR$ duplicator obtains more accurate results in a circuit with re- convergence paths, reducing the mean square errors by 64%- 94% compared to a conventional stochastic number duplicator.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130462855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability Estimations of Large Circuits in Massively-Parallel GPU-SPICE","authors":"Victor M. van Santen, H. Amrouch, J. Henkel","doi":"10.1109/IOLTS.2018.8474096","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474096","url":null,"abstract":"SPICE simulations for reliability have special requirements. We present GPU-SPICE to serve these special requirements. First, our GPU-SPICE employs the massive parallelism found in GPUs to enable circuit simulations beyond $200K$ transistors. This is necessary to study reliability in micro-architecture components (e.g., multipliers, adders), as reliability estimations require full analogue SPICE simulations (instead of STA or other heuristics). Secondly, our GPU-SPICE can update transistor parameters during the circuit simulation, a feature necessary to model reliability degradation, which constantly reacts to circuit activity (e.g., Bias Temperature Instability reacting to $V_{gs}$ changes by increasing/decreasing $Delta V_{th}$ in each transistor). Lastly, our GPU-SPICE is open-source software, this ensures that it easily can be employed, adapted and extended by other researchers. Due to the massive parallelism in a GPU and performance optimizations (convergence criteria, CUDA memory management, etc.), our GPU-SPICE is up to 218x faster than its single-threaded baseline NGSPICE.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130478148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Shielding Performance Monitor Counters: a double edged weapon for safety and security","authors":"Alberto Carelli, Alessandro Vallero, S. Carlo","doi":"10.1109/IOLTS.2018.8474191","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474191","url":null,"abstract":"Recent years have witnessed the growth of the adoption of Cyber-Physical Systems (CPSs) in many sectors such as automotive, aerospace, civil infrastructures and healthcare. Several CPS applications include critical scenarios, where a failure of the system can lead to catastrophic consequences. Therefore, anomalies due to failure or malicious attacks must be timely detected. This paper focuses on two relevant aspects of the design of a CPS: safety and security. In particular, it studies how performance monitor counters (PMCs) available in modern microprocessors can be from the one hand a valuable tool to enhance the safety of a system and, on the other hand, a security backdoor. Starting from the example of a PMC based safety mechanism, the paper shows the implementation of a possible attack and eventually proposes a strategy to mitigate the effectiveness of the attack while preserving the safeness of the system.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129736205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary","authors":"Petra R. Maier, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann","doi":"10.1109/IOLTS.2018.8474079","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474079","url":null,"abstract":"When used for safety-critical applications, embedded systems must behave safely at all times – even in the presence of random hardware faults. To ensure this, fault effect simulation by simulation-based fault injection is an integral part of embedded system development. The high complexity of embedded systems results in low simulation performance if all details of the system are simulated. Not simulating all details, i.e. increasing the simulation abstraction level, speeds up fault injection but can result in less accuracy in predicting the fault impacts on the system behavior. To achieve high accuracy and high simulation performance at the same time, we avoid simulation of details unrelated to the injected fault. For this, we divide the set of faults that can occur in an embedded system into three subsets. For each subset, we select the fault injection abstraction level of the embedded processor model that is as accurate as necessary but as fast as possible. The considered levels are host-compiled simulation, instruction set simulation and register transfer level simulation. For additional speed-up, the abstraction level can be switched during the fault injection simulation between register transfer and instruction set level. The fault set for host-compiled simulation can be reduced by static program analysis. Our results show that adapting the abstraction level to the fault set achieves high performance of the fault injection simulation.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123414323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis","authors":"Farah Naz Taher, Mostafa Kishani, Benjamin Carrión Schäfer","doi":"10.1109/IOLTS.2018.8474222","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474222","url":null,"abstract":"This work proposes an automatic method to generate opti- mized redundant hardware accelerator with maximum reliabil- ity given a single behavioral description for High-Level Syn- thesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over traditional RT- level design: The ability to generate micro-architectures with unique characteristics from the same behavioral description. This is typically done by setting different synthesis options to determine how to synthesize loops, arrays and functions and to specify the number and type of Functional Units (FUs) to be instantiated. The proposed method is composed of two main phases. The first phase performs HLS Design Space Exploration (DSE) leading to a trade-off curve of designs with a unique area, execution time and reliability. The second phase finds the most reliable system given an area and time constraint by either implementing time or space redundancy, or a mixture of both using any combinations of micro-architectures found by the explorer. This second phase has been formulated as an integer linear program (ILP). Experimental results show that the proposed method provides a 20% reliability increase compared to the most common approach of simply using a single micro-architecture and instantiating it multiple times with no significant area or timing overhead.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114955145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-cost functional test of a 2.4 GHz OQPSK transmitter using standard digital ATE","authors":"T. Vayssade, F. Azaïs, L. Latorre, F. Lefèvre","doi":"10.1109/IOLTS.2018.8474229","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474229","url":null,"abstract":"This paper presents a low-cost solution to implement a functional test for RF ZigBee transmitter. More precisely, the objective is to enable symbol error detection for a 2.4 GHz OQPSK-modulated signal with half sine pulse shaping on a digital ATE. The test is based on 1-bit under-sampled acquisition ofthe RF signal with a standard digital tester channel. A dedicated post-processing algorithm is then applied, which (i) extracts the phase information from the captured binary sequence, (ii) reconstructs the RF modulated signal and (iii) performs the demodulation. The different steps ofthe post-processing algorithm are detailed in this paper. Simulation and experimental results are presented, demonstrating the ability of the technique to correctly retrieve the emitted symbol sequence using only the binary data captured by the digital tester channel.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122521336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification","authors":"Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, H. Yotsuyanagi, M. Hashizume","doi":"10.1109/IOLTS.2018.8474268","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474268","url":null,"abstract":"Non-scan based test generation is required to reduce test cost and improve security. However, sequential test generation consumes a lot of time to identify untestable faults. Therefore, it is important to identify untestable faults in the preprocessing of the test generation. In this paper, an unreachable state identification method, which identifies whether states on a few flip-flops can be justified using SAT, and an untestable fault identification method using the unreachable states are proposed. Experimental results show that our proposed method was effective compared with conventional methods.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122095259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IOLTS 2018 Index","authors":"","doi":"10.1109/iolts.2018.8474147","DOIUrl":"https://doi.org/10.1109/iolts.2018.8474147","url":null,"abstract":"","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116731907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation","authors":"Ioannis Tsiokanos, L. Mukhanov, Dimitrios S. Nikolopoulos, G. Karakonstantis","doi":"10.1109/IOLTS.2018.8474084","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474084","url":null,"abstract":"The continuous scaling of transistor sizes and the increased static and dynamic parametric variations render nanometer circuits more prone to timing failures. To protect circuits from such failures, typically designers adopt pessimistic timing margins, which are estimated statically under rare worst-case conditions. In this paper, we aim at minimizing the timing failures, while avoiding such pessimistic margins by proposing an approach that initially minimizes the number of long latency paths within each processor pipeline stage and con- straints them in as few stages as possible. Such an approach, not only reduces the timing failures, but also limits the potential error prone locations to only few pipeline registers/stages. To further reduce these failures, we exploit the path excitation dependence on data patterns and we truncate the bit-width of the operands in the few remaining long latency paths by setting a number of least significant bits to a constant value zero. Such truncation may incur quality loss, but this can be controlled by carefully selecting the number of truncated bits and will be in any case less than the catastrophic loss that may be incurred under random timing failures. Additionally, our framework performs post- place and route dynamic timing analysis based on real operands that are extracted from a variety of applications, helping to estimate the dynamic timing failures, while considering the data dependent path excitation. When applied to an IEEE-754 compatible double precision Floating Point Unit (FPU), the proposed approach reduces the timing failures by $104.5times$ on average compared to a reference FPU design under an assumed 8.1% variation-induced worst-case path delay increase in a 45 nm process. Finally, results show that path shaping alone introduces an insignificant 0.25% area and 5.7% power overhead with no performance cost. The combination of path shaping with aggressive operand bit- width truncation leads to up-to 44.7% on average power savings due to the substantially reduced switching activity at a minimal quality loss.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130657866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}