Reliability Estimations of Large Circuits in Massively-Parallel GPU-SPICE

Abstract

SPICE simulations for reliability have special requirements. We present GPU-SPICE to serve these special requirements. First, our GPU-SPICE employs the massive parallelism found in GPUs to enable circuit simulations beyond $200K$ transistors. This is necessary to study reliability in micro-architecture components (e.g., multipliers, adders), as reliability estimations require full analogue SPICE simulations (instead of STA or other heuristics). Secondly, our GPU-SPICE can update transistor parameters during the circuit simulation, a feature necessary to model reliability degradation, which constantly reacts to circuit activity (e.g., Bias Temperature Instability reacting to $V_{gs}$ changes by increasing/decreasing $\Delta V_{th}$ in each transistor). Lastly, our GPU-SPICE is open-source software, this ensures that it easily can be employed, adapted and extended by other researchers. Due to the massive parallelism in a GPU and performance optimizations (convergence criteria, CUDA memory management, etc.), our GPU-SPICE is up to 218x faster than its single-threaded baseline NGSPICE.