Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis

This work proposes an automatic method to generate opti- mized redundant hardware accelerator with maximum reliabil- ity given a single behavioral description for High-Level Syn- thesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over traditional RT- level design: The ability to generate micro-architectures with unique characteristics from the same behavioral description. This is typically done by setting different synthesis options to determine how to synthesize loops, arrays and functions and to specify the number and type of Functional Units (FUs) to be instantiated. The proposed method is composed of two main phases. The first phase performs HLS Design Space Exploration (DSE) leading to a trade-off curve of designs with a unique area, execution time and reliability. The second phase finds the most reliable system given an area and time constraint by either implementing time or space redundancy, or a mixture of both using any combinations of micro-architectures found by the explorer. This second phase has been formulated as an integer linear program (ILP). Experimental results show that the proposed method provides a 20% reliability increase compared to the most common approach of simply using a single micro-architecture and instantiating it multiple times with no significant area or timing overhead.