2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)最新文献

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A New Approach to Threshold Voltage Measurements of Transistors 一种新的晶体管阈值电压测量方法
Theodor Hillebrand, S. Paul, D. Peters-Drolshagen
{"title":"A New Approach to Threshold Voltage Measurements of Transistors","authors":"Theodor Hillebrand, S. Paul, D. Peters-Drolshagen","doi":"10.1109/IOLTS.2018.8474086","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474086","url":null,"abstract":"In this paper an on-line monitoring method for the threshold voltage of MOSFETs is presented. A state space model of the device under test is pre-fitted and used within a particle filter algorithm. The method is capable of extracting the threshold voltage in arbitrary mission or stress conditions. Thus, for reliability assessments the stress does not have to be relieved in order to measure a shift of the threshold voltage. Moreover, the monitoring is able to cancel out certain environmental influences such as temperature and supply voltage fluctuations which is a major improvement for any reliability assessment. The method is evaluated with TCAD (FDSOI Transistor) and SPICE (CMOS Transistor) simulations.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114733155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
IOLTS 2018 Technical Papers IOLTS 2018技术论文
{"title":"IOLTS 2018 Technical Papers","authors":"","doi":"10.1109/iolts.2018.8474099","DOIUrl":"https://doi.org/10.1109/iolts.2018.8474099","url":null,"abstract":"","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126453871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power/Area-Optimized Fault Tolerance for Safety Critical Applications 安全关键应用的功率/面积优化容错
M. Krstic, A. Simevski, Markus Ulbricht, S. Weidling
{"title":"Power/Area-Optimized Fault Tolerance for Safety Critical Applications","authors":"M. Krstic, A. Simevski, Markus Ulbricht, S. Weidling","doi":"10.1109/IOLTS.2018.8474178","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474178","url":null,"abstract":"Increasing the reliability of a system always comes with a high price in performance/power/area overhead. Enabling error detection and correction features can be obtained by employing different kinds of redundancy including hardware, time, information, software or some combination of them. In many cases the imposed overhead is enormous. Fault tolerance is an important requirement for safety critical applications (e.g., automated driving), but significant power/area overhead is not acceptable. This paper summarizes several strategies and methods how to reduce the introduced overhead, while still providing a respectable level of fault tolerance features. Two main methodologies are discussed: static and dynamic. Static methods address the overhead by performing a static trade-off between the achieved level of fault tolerance and the introduced overhead. Dynamic methods on the other hand are based on the actual application requirement, and are dynamically varying the required overhead to fulfill the safety requirements of the application. This paper summarizes practical examples and results in this field.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130121140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ESIFT: Efficient System for Error Injection ESIFT:有效的错误注入系统
Ninghan Tian, D. Saab, J. Abraham
{"title":"ESIFT: Efficient System for Error Injection","authors":"Ninghan Tian, D. Saab, J. Abraham","doi":"10.1109/IOLTS.2018.8474160","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474160","url":null,"abstract":"Computer use in high dependability applications is rapidly increasing. These applications require the computer to be able to detect, locate, isolate and recover from software, hardware or security attacks errors. To evaluate the dependability of a computer system design, it is critical to be able to assess its ability to detect, locate, recover from errors, and to estimate coverage and latencies. Fault-injection tools play critical role in the evaluation and validation of dependable systems. They generate statistics on error coverage and latencies. This helps to identify good fault tolerance technique that detects and prevent system failures. In this paper, we present an Efficient Fault Injection System for Transient Fault (ESIFT). ESIFT is based on Python extended GDB which makes ESIFT portable across a wide variety of systems. ESFIT operates at near native speed enabling the dependability evaluation of large system. Unlike traditional techniques which evaluate only the faulty system behavior, ESIFT evaluates, concurrently, both the faulty and the fault-free system behavior. This allows faster error detection and latency evaluation.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131119019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
IOLTS 2018 Commentary IOLTS 2018解说
{"title":"IOLTS 2018 Commentary","authors":"","doi":"10.1109/iolts.2018.8474094","DOIUrl":"https://doi.org/10.1109/iolts.2018.8474094","url":null,"abstract":"","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121929050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Tradeoffs in Bioimplantable Devices: A Case Study with Bladder Pressure Monitoring 生物植入装置的设计权衡:膀胱压力监测的案例研究
Shakil Mahmud, S. Majerus, M. Damaser, Robert Karam
{"title":"Design Tradeoffs in Bioimplantable Devices: A Case Study with Bladder Pressure Monitoring","authors":"Shakil Mahmud, S. Majerus, M. Damaser, Robert Karam","doi":"10.1109/IOLTS.2018.8474106","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474106","url":null,"abstract":"Acceptable design tradeoffs depend heavily on the environment in which a device will operate. For bioimplantable devices, area, power, and reliability are crucial considerations which can dramatically impact their design, implementation, and eventual clinical translation. In this paper, we discuss potential effects of such tradeoffs using a wireless implantable bladder pressure sensor as a case study. We note that low power design techniques such as clock and power gating, when coupled with a reliable process technology, can improve device reliability while meeting the stringent area and power constraints of wireless biomedical implants.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123828102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server 考虑商品服务器内系统级效应的放松刷新周期下的DRAM特性
L. Mukhanov, Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, G. Karakonstantis
{"title":"DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server","authors":"L. Mukhanov, Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, G. Karakonstantis","doi":"10.1109/IOLTS.2018.8474184","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474184","url":null,"abstract":"Today’s rapid generation of data and the increased need for higher memory capacity has triggered a lot of studies on aggressive scaling of refresh period, which is currently set according to rare worst case conditions. Such studies analysed in detail the data-dependent circuit level factors and indicated the need for online DRAM characterization due to the variable cell retention time. They have done so by executing few test data patterns on FPGAs under controlled temperatures by using thermal testbeds, which however cannot be available in the field. Moreover, the existing studies were not able to reveal any system level effects, which may be excited under the execution of workloads on real systems and directly or indirectly affect DRAM reliability. In this paper, we develop an experimental framework based on a state-of-the-art 64-bit ARM based server with Linux OS, in which we enabled the DRAM characterization under relaxed refresh period by executing conventional test data patterns as well as popular HPC and Cloud workloads. Our results indicate that common test patterns are ineffective in identifying error-prone locations at low DRAM temperatures. Furthermore, we reveal that there is a strong correlation between the SOC utilization and DRAM reliability. By exploiting such findings, we developed a benchmark, which can indirectly stress the DRAM temperature and thus used for characterization in the field without needing any complicated thermal equipment. Our study shows that the refresh period can be relaxed by 35 times on such a commodity system with all errors being corrected by the available error correcting codes, resulting in 11.5% power savings on average.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121605899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
IOLTS 2018 About IOLTS Page IOLTS 2018关于IOLTS页面
{"title":"IOLTS 2018 About IOLTS Page","authors":"","doi":"10.1109/iolts.2018.8474252","DOIUrl":"https://doi.org/10.1109/iolts.2018.8474252","url":null,"abstract":"","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134372016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IOLTS 2018 External Reviewers IOLTS 2018外部审稿人
{"title":"IOLTS 2018 External Reviewers","authors":"","doi":"10.1109/iolts.2018.8474239","DOIUrl":"https://doi.org/10.1109/iolts.2018.8474239","url":null,"abstract":"","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134642387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation 独立的n井和p井偏置最小泄漏能量运行
Yosuke Okamura, T. Ishihara, H. Onodera
{"title":"Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation","authors":"Yosuke Okamura, T. Ishihara, H. Onodera","doi":"10.1109/IOLTS.2018.8474128","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474128","url":null,"abstract":"This paper proposes a method for minimizing leakage energy consumption under a specific supply voltage and a delay constraint by independently tuning threshold voltages of nMOSFETs and pMOSFETs with body-biasing. We first show a necessary and sufficient condition for the minimum leakage energy operation of a circuit under a delay constraint. We next show that the condition can be identified by a ratio of the leakage currents drawn through an nMOSFET and a pMOSFET in a leakage monitor circuit integrated with the targeting circuit. The leakage current ratio can be monitored at runtime using the leakage monitor. Assuming a constant supply voltage, it is thus possible to minimize the total energy consumption of the circuit by independent tuning of n-well and p-well bias voltages so that the leakage current ratio tracks the predetermined value while keeping the delay constraint. The proposed strategy is experimentally verified by measurements using a 32-bit RISC processor integrating the leakage monitor on the same die fabricated with a 65 nm CMOS process.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116093663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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