独立的n井和p井偏置最小泄漏能量运行

Yosuke Okamura, T. Ishihara, H. Onodera
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引用次数: 0

摘要

本文提出了一种在特定电源电压和延迟约束下,通过体偏调谐nmosfet和pmosfet的阈值电压来最小化泄漏能量消耗的方法。首先给出了电路在时滞约束下最小漏能运行的充分必要条件。我们接下来表明,该条件可以通过泄漏监测电路中与目标电路集成的nMOSFET和pMOSFET绘制的泄漏电流的比率来识别。漏电监测器可以在运行时监测漏电流比。假设电源电压恒定,则可以通过独立调谐n井和p井偏置电压来最小化电路的总能耗,从而使漏电流比跟踪预定值,同时保持延迟约束。采用32位RISC处理器集成了泄漏监测器,并采用65nm CMOS工艺在同一芯片上进行了实验验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation
This paper proposes a method for minimizing leakage energy consumption under a specific supply voltage and a delay constraint by independently tuning threshold voltages of nMOSFETs and pMOSFETs with body-biasing. We first show a necessary and sufficient condition for the minimum leakage energy operation of a circuit under a delay constraint. We next show that the condition can be identified by a ratio of the leakage currents drawn through an nMOSFET and a pMOSFET in a leakage monitor circuit integrated with the targeting circuit. The leakage current ratio can be monitored at runtime using the leakage monitor. Assuming a constant supply voltage, it is thus possible to minimize the total energy consumption of the circuit by independent tuning of n-well and p-well bias voltages so that the leakage current ratio tracks the predetermined value while keeping the delay constraint. The proposed strategy is experimentally verified by measurements using a 32-bit RISC processor integrating the leakage monitor on the same die fabricated with a 65 nm CMOS process.
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