2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)最新文献_第3页

A Capture Safe Static Test Compaction Method Based on Don't Cares 一种基于不在乎的捕获安全静态测试压实方法

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474080

Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura

引用次数: 0

Efficient Software-Based Partitioning for Commercial-off-the-Shelf NoC-based MPSoCs for Mixed-Criticality Systems 用于混合临界系统的商用现成的基于noc的mpsoc的高效软件分区

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474155

Stefano Esposito, Serhiy Avramenko, M. Violante

{"title":"Efficient Software-Based Partitioning for Commercial-off-the-Shelf NoC-based MPSoCs for Mixed-Criticality Systems","authors":"Stefano Esposito, Serhiy Avramenko, M. Violante","doi":"10.1109/IOLTS.2018.8474155","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474155","url":null,"abstract":"Some industrial domains, characterized by particularly strict safety standards – e.g., avionics – are facing issues when addressing the usage of commercial-off-the-shelf multi-processor system-on-chips and in particular new network-on-chip-based architectures. One key issue is related to the usage of such system-on-chips to implement mixed-criticality systems with the main goal of reducing size, weight, and power consumption of on-board equipment by reducing the number of computers moving from federated architectures based on singlecore processors to a single multi-core processor. To comply with relevant safety standards, a mixed-criticality system should be proven to enforce isolation among safety-critical and non-safetycritical tasks running on the multi-core hardware platform. This paper presents a software-level methodology tackling such issue. The proposed methodology exploits knowledge of the deterministic routing algorithm used by the network-on-chip to implement a safe and efficient partitioning of the system. This paper presents the software implementation and an experimental evaluation of the solution, proving its suitability for integration in an avionic application.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121371687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Test Compression Using Extended Nonlinear Binary Codes 使用扩展非线性二进制码的测试压缩

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474242

O. Novák

引用次数: 0

Integrated Test Structures for Reliability Investigation under Dynamic Stimuli 用于动态刺激下可靠性研究的集成测试结构

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474074

F. Cacho, D. Nouguier, M. Arabi, X. Federspiel, Y. Carminati, M. Saliva

引用次数: 5

Reliability And Performance Challenges Of Ultra-Low Voltage Caches: A Trade-Off Analysis 超低电压高速缓存的可靠性和性能挑战:权衡分析

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474272

A. Gebregiorgis, M. Tahoori

引用次数: 1

About the functional test of the GPGPU scheduler 关于GPGPU调度程序的功能测试

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474174

B. Du, J. E. R. Condia, M. Reorda, L. Sterpone

{"title":"About the functional test of the GPGPU scheduler","authors":"B. Du, J. E. R. Condia, M. Reorda, L. Sterpone","doi":"10.1109/IOLTS.2018.8474174","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474174","url":null,"abstract":"General Purpose Graphical Processing Units (GPGPUs) are increasingly used in safety critical applications such as the automotive ones. Hence, techniques are required to test them during the operational phase with respect to possible permanent faults arising when the device is already deployed in the field. Functional tests adopting Software-based Self-test (SBST) are an effective solution since they provide benefits in terms of intrusiveness, flexibility and test duration. While the development of the functional test code addressing the several computational cores composing a GPGPU can be done resorting to known methods developed for CPUs, for other modules which are typical of a GPGPU we still miss effective solutions. This paper focuses on one of the most relevant module consists on the scheduler core which is in charge of managing different scalar computational cores and the different executed threads. At first, we propose a method for evaluating the fault coverage that can be achieved using an application program. Then, we provide some guidelines for improving the achieved fault coverage. Experimental results are provided on an open-source VHDL model of a GPGPU.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130517175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Resistive and Spintronic RAMs: Device, Simulation, and Applications 电阻和自旋电子ram:器件、仿真和应用

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474226

E. Vatajelu, L. Anghel, J. Portal, M. Bocquet, G. Prenat

{"title":"Resistive and Spintronic RAMs: Device, Simulation, and Applications","authors":"E. Vatajelu, L. Anghel, J. Portal, M. Bocquet, G. Prenat","doi":"10.1109/IOLTS.2018.8474226","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474226","url":null,"abstract":"The emergence of non-volatile random access memory technologies, such as resistive and spintronic RAMs are triggering intense interdisciplinary activity. These technologies have the potential of providing many benefits, such as energy efficiency, high integration density, CMOS-compatibility, re-configurability, non-volatility and open the path towards novel computational structures and approaches, for the traditional Von-Neumann architectures and beyond. These promising characteristics, coupled with the ever-increasing limitations faced by traditional CMOS-based storage and computational structures, have driven the research community towards completely revisiting the existing computing and storage paradigms, now focusing on providing hardware solutions for in-memory and neuromorphic computing. This has resulted in an intensified research activity in the device physics, striving to achieve circuit-worth devices, reliable compact models and novel architectures. The purpose of this paper is to provide a comprehensive overview of the device physics, issues related to its use in electronic circuits, methodologies for their compact modelling and simulations, and their integration in storage and computational structures.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"35 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131575097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

IOLTS 2018 Welcome Message IOLTS 2018欢迎辞

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/iolts.2018.8474227

引用次数: 0

Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard 朝着根据ISO 26262功能安全标准自动进行硬件验证的方向发展

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474083

J. Sini, M. Reorda, M. Violante, Peter Sarson

引用次数: 0

Fault-Resilient Topology Planning and Traffic Configuration for IEEE 802.1Qbv TSN Networks IEEE 802.1Qbv TSN网络的故障恢复拓扑规划与流量配置

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474201

Ayman A. Atallah, Ghaith Bany Hamad, O. Mohamed

{"title":"Fault-Resilient Topology Planning and Traffic Configuration for IEEE 802.1Qbv TSN Networks","authors":"Ayman A. Atallah, Ghaith Bany Hamad, O. Mohamed","doi":"10.1109/IOLTS.2018.8474201","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474201","url":null,"abstract":"Time-Sensitive Networking (TSN) is a set of IEEE standards that are being developed to enable a reliable and real-time communication based on Ethernet technology. It supports Time-Triggered (TT) traffic to allow a low latency as well as deterministic timing behavior. TSN adapts the concept of seamless redundancy to ensure interruption-free fault-resilience. In this paper, our goal is to synthesize a network topology that supports seamless redundant transmission for TT messages. Therefore, we propose a greedy heuristic algorithm for joint topology, routing, and schedule synthesis. The proposed algorithm is capable to generate fault-resilient topology that guarantee feasible routing and scheduling for TT traffic. In particular, the topology is constructed iteratively such that all messages are routed through disjoint paths with a feasible schedule and the network cost is minimized. To achieve this goal, we formulate the topology synthesis problem as iterative path selection problem. Starting from a weighted undirected graph which represents an initial fully-connected network, the cost implied of using each link is mapped as arcs weights in the graph. Then, we adapt Yen's algorithm to iteratively find the minimum-cost paths for the considered messages. The scalability and the efficiency of the proposed approach are demonstrated using 380 synthetic test cases. The results show that the proposed approach is capable of finding fault-resilient topology with up to 50% less cost compared to the typical approach. Moreover, the approach scalability is validated e.g., it handles 24 ECUs with 600 messages problems within an average time of 8 sec.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133291015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30