2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)最新文献

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CMOS Characterization and Compact Modelling for Circuit Reliability Simulation 电路可靠性仿真的CMOS特性和紧凑建模
J. Diaz-Fortuny, J. Martín-Martínez, R. Rodríguez, M. Nafría, R. Castro-López, E. Roca, F. Fernández
{"title":"CMOS Characterization and Compact Modelling for Circuit Reliability Simulation","authors":"J. Diaz-Fortuny, J. Martín-Martínez, R. Rodríguez, M. Nafría, R. Castro-López, E. Roca, F. Fernández","doi":"10.1109/IOLTS.2018.8474244","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474244","url":null,"abstract":"With nowadays nanometer-CMOS technologies, time-zero and time dependent variability effects (like BTI, CHI, RTN, TDDB, EM, etc) have turned into an even more serious threat to the desired performance of analog and digital integrated circuits. Statistical characterization and modelling of these variability effects entail large testing times, which are typically prohibitive, and huge amounts of data, which are complex to post process. This paper describes novel characterization techniques that overcome these limitations, that is, they are capable of statistically testing nanometer CMOS devices with much shorter completion times. To properly handle the massive amounts of data from characterization, new extraction methods, described in this paper as well, have been developed. With these methods, an accurate variability-aware device model is completed, which can subsequently be used in reliability-aware circuit design methodologies.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128504188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Robust Machine Learning Systems: Reliability and Security for Deep Neural Networks 鲁棒机器学习系统:深度神经网络的可靠性和安全性
Muhammad Abdullah Hanif, Faiq Khalid, Rachmad Vidya Wicaksana Putra, Semeen Rehman, M. Shafique
{"title":"Robust Machine Learning Systems: Reliability and Security for Deep Neural Networks","authors":"Muhammad Abdullah Hanif, Faiq Khalid, Rachmad Vidya Wicaksana Putra, Semeen Rehman, M. Shafique","doi":"10.1109/IOLTS.2018.8474192","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474192","url":null,"abstract":"Machine learning is commonly being used in almost all the areas that involve advanced data analytics and intelligent control. From applications like Natural Language Processing (NLP) to autonomous driving are based upon machine learning algorithms. An increasing trend is observed in the use of Deep Neural Networks (DNNs) for such applications. While the slight inaccuracy in applications like NLP does not have any severe consequences, it is not the same for other safety-critical applications, like autonomous driving and smart healthcare, where a small error can lead to catastrophic effects. Apart from high-accuracy DNN algorithms, there is a significant need for robust machine learning systems and hardware architectures that can generate reliable and trustworthy results in the presence of hardware-level faults while also preserving security and privacy. This paper provides an overview of the challenges being faced in ensuring reliable and secure execution of DNNs. To address the challenges, we present several techniques for analyzing and mitigating the reliability and security threats in machine learning systems.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134406760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Collective-Aware System-on-Chips for Dependable IoT Applications 用于可靠物联网应用的集体感知芯片系统
V. Tenentes, Daniele Rossi, B. Al-Hashimi
{"title":"Collective-Aware System-on-Chips for Dependable IoT Applications","authors":"V. Tenentes, Daniele Rossi, B. Al-Hashimi","doi":"10.1109/IOLTS.2018.8474172","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474172","url":null,"abstract":"IoT applications with low-budget connected nodes are emerging for a variety of domains, such as smart cities, geomonitoring, parking sensors, surveillance etc. These low-cost nodes contain System-on-Chips (SoCs) with networking capabil- ities. In this paper, we propose to exploit this feature for their dependability management. In particular, we propose collective- awareness, which is a run-time system that emerges when cloud resources are provided to the SoCs for IoT applications for storing information related to their in-the-field status, such as preferable operating modes and performance degradation. Periodically, a dynamic dependability model is constructed by the collected data and SoCs software is updated to meet user-defined lifetime, reliability and performance requirements. To evaluate the operations of the proposed system, we emulate the in-the- field performance degradation of a fleet of a 10K IoT nodes using Monte Carlo on temperature and workload conditions using the largest IWLS’05 benchmarks. During the first two years of system operation, the dynamically constructed model performs lifetime estimation with up to 57% higher accuracy, compared to a static model that considers data only from the design phase of the circuits, while after three years the dynamic model is always accurate for all the devices.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133964059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Automatic Approach to Perform FMEDA Safety Assessment on Hardware Designs 一种对硬件设计进行FMEDA安全评估的自动方法
J. Sini, M. Violante
{"title":"An Automatic Approach to Perform FMEDA Safety Assessment on Hardware Designs","authors":"J. Sini, M. Violante","doi":"10.1109/IOLTS.2018.8474217","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474217","url":null,"abstract":"Electronic control units have a central role in almost all the function of road vehicles. Some of these functions are safety critical so, during their development, it is requested by standards, like ISO 26262, to follow strict design rules and to perform in-depth verification steps. One of the technique recommended during the hardware design process is the failure mode, effect and diagnostic analysis (FMEDA). In industrial practice, this technique is manually applied by the designer by inspecting the circuit schematics, but in this way, the process is error-prone and make it difficult to take in proper consideration the contribution of the embedded software. In literature, it is possible to find some attempts to automate the FMEDA process. This article discusses a novel approach that allows reducing the time needed to perform FMEA and improving the quality of the achieved results.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122000684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Finding False Paths for Sequential Circuits Using Operations on ROBDDs 利用对robdd的操作发现顺序电路的假路径
A. Matrosova, S. Ostanin, S. Chernyshov
{"title":"Finding False Paths for Sequential Circuits Using Operations on ROBDDs","authors":"A. Matrosova, S. Ostanin, S. Chernyshov","doi":"10.1109/IOLTS.2018.8474213","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474213","url":null,"abstract":"Performance of VLSI is, first of all, its high operation speed determined by a clock frequency. Developing of VLSI is oriented to maximal possible clock frequency under correct functioning. Clock frequency estimation is reduced to finding paths with maximal delays (critical paths) among logical components of VLSI. But some of the selected paths may be false. It means that the path has no impact on component functioning. It is necessary to fmd such paths in order to exclude them from consideration when we determine clock frequency. Detecting false paths may increase VLSI operation speed. The precise method of fmding false paths in a sequential circuit based on finding test pairs for non-robust path delay faults (PDFs) is developed. The length of a transfer sequence delivering the test pair from the initial internal state is not more the given value l. The method is based on applying operations on ROBDDs extracted from the combinational part of a sequential circuit. Experimental results illustrate the suggested method.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127440257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter 使用内置增量∑Δ转换器的SAR adc的减码静态线性测试
R. Feitoza, M. Barragán, S. Mir, D. Dzahini
{"title":"Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter","authors":"R. Feitoza, M. Barragán, S. Mir, D. Dzahini","doi":"10.1109/IOLTS.2018.8474180","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474180","url":null,"abstract":"This work presents a strategy for static linearity self-testing of successive-approximation analog to digital converters (SAR ADCs) with the goal of reducing test time. The proposed test technique takes advantage of the SAR ADC architecture to drastically reduce the number of necessary measurements for a complete static linearity characterization. Moreover, we show that static linearity measurements can be performed on-chip without the need of a test stimulus generator, by generating the major carrier transitions of the SAR ADC and acquiring them with a low resolution ADC. The proposed test circuitry is reduced to a simple incremental ∑Δ ADC. The technique is validated with behavioral simulations and the design trade-offs of the proposed test circuitry are explored.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121366142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Near-Optimal Node Selection Procedure for Aging Monitor Placement 老化监测仪布置的近最优节点选择程序
Somayeh Sadeghi Kohan, Arash Vafaei, Z. Navabi
{"title":"Near-Optimal Node Selection Procedure for Aging Monitor Placement","authors":"Somayeh Sadeghi Kohan, Arash Vafaei, Z. Navabi","doi":"10.1109/IOLTS.2018.8474120","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474120","url":null,"abstract":"Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to severalprocessors and ITC benchmarks and have looked at its effectiveness for these circuits.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122515372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm 基于栅极尺寸和多目标粒子群优化算法的组合电路软误差优化
Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Jiaqiang Li, Jinxiang Wang
{"title":"Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm","authors":"Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li, Jiaqiang Li, Jinxiang Wang","doi":"10.1109/IOLTS.2018.8474275","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474275","url":null,"abstract":"Soft errors caused by particle strike in combinational circuits are a major concern in the design of reliable circuits. Particle strike induced single event transient (SET), especially the evolutional single event multiple transients (SEMTs) in nanoscale CMOS technologies, has been the non-negligible reliability issue for hardening design of combinational circuits. This paper presents a low overhead method to protect combinational circuits against particle strike. This method is made up of a combination of two sub-method: (1) a soft error sensitivity estimation method, called Layout-Based Multiple Event Probability Propagation (LBMEPP) and (2) a protection method based on gate sizing, called Intelligent optimization-Based Gate Sizing (IOBGS). Unlike the previous techniques that either overlook the SEMTs event or exploit fault injection. LBMEPP can provide the sensitivity estimation of combinational circuits in the presence of SET and SEMTs. The SEMTs adjacent cells are identified by the cell’s layout and Geant4 Monte Carlo simulation. Therefore, the SEMTs event can be considered in the sensitivity estimation. Using the estimation result of LBMEPP, IOBGS adopts multi-objective particle swarm optimization algorithm to dynamically allocate and adjust each logical cells. In IOBGS, SER, circuit area and longest path delay of the circuit are selected as the optimization goals. The experiments conducted on several typical circuits show that the proposed optimization method can evidently decrease the SER with a limited overhead.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123200564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
HealthLog Monitor: A Flexible System-Monitoring Linux Service HealthLog Monitor:一个灵活的系统监控Linux服务
Athanasios Chatzidimitriou, G. Papadimitriou, D. Gizopoulos
{"title":"HealthLog Monitor: A Flexible System-Monitoring Linux Service","authors":"Athanasios Chatzidimitriou, G. Papadimitriou, D. Gizopoulos","doi":"10.1109/IOLTS.2018.8474119","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474119","url":null,"abstract":"Error monitoring is a critical procedure for most computing systems, varying from HPC to embedded systems domains. Several generic architectures have been proposed and employed in modern processors, offering the capability of hardware-level error detection. This critical information is required to isolate and/or mitigate failures. However, research has revealed many cases where indications of upcoming failures can be identified early and before the actual fail occurrence, known as symptoms. Such cases become more frequent as technology trends try to exploit the conservative worst-case voltage guardbands and push computing systems towards more aggressive and often hazardous regions. In this paper we present HealthLog monitor, a flexible system monitoring service that offers a generic abstraction layer to combine both error and symptom monitoring. HealthLog is capable of monitoring hardware measurements (performance, sensor and errors) as well as external health-related data, allowing combined symptom description and reaction features supported by an API. The scope of the monitor is to offer a universal standard for error reporting and system monitoring mechanisms in all system layers. The current version of HealthLog was developed and tested on AppliedMicro’s X-Gene 2 micro-server, but it is a cross-platform solution as it does not depend on a specific architecture. This work demonstrates how platform events, software metrics and external peripheral mechanisms can be combined to deliver early warnings of upcoming failures and trigger evading reactions.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123480958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
From on-chip self-healing to self-adaptivity in analog/RF ICs: challenges and opportunities 从片上自愈到模拟/射频集成电路的自适应:挑战与机遇
M. Andraud, M. Verhelst
{"title":"From on-chip self-healing to self-adaptivity in analog/RF ICs: challenges and opportunities","authors":"M. Andraud, M. Verhelst","doi":"10.1109/IOLTS.2018.8474078","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474078","url":null,"abstract":"The numerous variations that affect analog and RF circuits are becoming a limiting factor in the design of these circuits in deeply scaled CMOS technologies. An emerging idea to counteract these effects is to let the circuit compensate for these variations itself, referred to as self-healing. Over the last decade, a wide variety of off- and on-chip techniques for compensating these variations have been researched. This paper targets to give an overview of the state-of-the-art, and organize the proposed techniques in a common taxonomy. This allows to determine remaining open issues and research challenges. In particular, the SotA lacks efficient solutions for fully-integrated, short time-scale self-adaptation. The paper ends by giving an outlook towards promising research directions to enable such self-adaptation in mWatt power budgets for Internet of things applications, focusing on embedded machine-learning techniques.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122905423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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