2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)最新文献_第5页

Resistive Switching Behavior seen from the Energy Point of View 从能量的角度看电阻开关行为

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474167

Jorge Gomez, Angel Abusleme, I. Vourkas, A. Rubio

{"title":"Resistive Switching Behavior seen from the Energy Point of View","authors":"Jorge Gomez, Angel Abusleme, I. Vourkas, A. Rubio","doi":"10.1109/IOLTS.2018.8474167","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474167","url":null,"abstract":"The technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied pulse characteristics, such as amplitude and duration. However, parameter variability holds back any universal approach based on these two magnitudes, making also difficult even the qualitative comparison between different RS material compounds. On the contrary, there is a relevant magnitude which is much less affected by device variability; the energy. In this direction, we doubt anyone so far has ever wondered “what is the quantitative effect of the injected energy on the device state?” Interestingly, a first step was made recently towards the definition of performance parameters for this emerging device technology, using as fundamental parameter the energy. In this work, we further elaborate on such ideas, proving experimentally that the “resistance change per energy unit” $( dR/ dE )$ can be considered a significant magnitude in analog operation of bipolar memristors, being a key performance parameter worth of timely disclosure.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126600114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling 基于健康感知任务调度的多处理器系统可靠性改进

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474101

Robert Schmidt, Rehab Massoud, J. Raik, A. Ortiz, R. Drechsler

引用次数: 2

Hardware and Software Techniques for Heterogeneous Fault-Tolerance 异构容错的硬件和软件技术

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474219

Semeen Rehman, F. Kriebel, B. Prabakaran, Faiq Khalid, M. Shafique

{"title":"Hardware and Software Techniques for Heterogeneous Fault-Tolerance","authors":"Semeen Rehman, F. Kriebel, B. Prabakaran, Faiq Khalid, M. Shafique","doi":"10.1109/IOLTS.2018.8474219","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474219","url":null,"abstract":"With the advancements in the process technology, fault-tolerance against transient errors has emerged as an important design requirement for computing systems fabricated using nano-scale devices. Traditionally, redundancy-based techniques have been employed to detect and correct errors, and to achieve full system protection. However, as fault masking properties on different system levels have been observed and applications with lower accuracy demands or error-tolerant properties exist, reliability-heterogeneous architectures have recently paved the way for power-efficient dependable systems. In this paper, we will discuss the building blocks of such processors (both embedded and superscalar) with different fault-tolerant modes on the architecture level covering memory components like caches as well as in-order and out-of-order processor designs. We analyze the soft error vulnerability of different components and show how the variations in vulnerabilities can be exploited to improve the performance and power efficiency of such processors. We additionally show that a reliability-driven compiler can be leveraged to realize software-level heterogeneous fault tolerance by generating different reliable application versions with diverse reliability and performance properties.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125811125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues 激光脉冲对STT-MRAM位元的影响:安全性和可靠性问题

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474088

Mounia Kharbouche-Harrari, J. Postel-Pellerin, G. D. Pendina, R. Wacquez, Driss Aboulkassimi, M. Bocquet, R. Sousa, R. Delattre, J. Portal

引用次数: 5

Robust co-synthesis of embedded control systems with occasional deadline misses 偶尔错过截止日期的嵌入式控制系统鲁棒协同综合

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474138

A. Behrouzian, Dip Goswami, T. Basten

引用次数: 2

A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns 一种基于控制器增强的测试寄存器分配方法以减少测试模式的数量

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474097

Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura

引用次数: 2

Development flow of on-line Software Test Libraries for asynchronous processor cores 异步处理器核心在线软件测试库的开发流程

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474126

A. Floridia, E. Sánchez, Nikolaos Andrikos

{"title":"Development flow of on-line Software Test Libraries for asynchronous processor cores","authors":"A. Floridia, E. Sánchez, Nikolaos Andrikos","doi":"10.1109/IOLTS.2018.8474126","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474126","url":null,"abstract":"Asynchronous design style is quite appealing from various perspectives. In particular, several studies confirmed the reliability of asynchronous circuits in harsh environments, being capable to better tolerate power supply and temperature variations with respect to their synchronous counterparts. However, despite these advantages and many others, their applicability (especially in safety-critical scenarios) is quite limited today. Additionally, commercial EDA tools can be hardly used for asynchronous designs; hence, designers are discouraged of using such approaches for their applications. Notably, devices deployed for safety-critical applications must satisfy stringent requirements in order to guarantee the highest level of functional safety. Commonly, on-line testing mechanisms are necessary to achieve standards compliance. Such mechanisms undergo a validation process to assess their effectiveness, fault injection campaigns being the most commonly used. For doing so, designers exploit commercial EDA tools, intended to certificate standard compliance. In this paper, a methodology for the validation of Software Test Libraries (STLs) targeting on-line testing of asynchronous processor cores is proposed. The methodology is based exclusively on commercial tools, currently used in industry for functional safety analysis.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126055366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Detecting and Resolving Security Violations in Reconfigurable Scan Networks 在可重构扫描网络中检测和解决安全违规

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474188

Pascal Raiola, M. Kochte, A. Atteya, Laura Rodríguez Gómez, H. Wunderlich, B. Becker, M. Sauer

引用次数: 10

On the test of a COTS-based system for space applications 关于基于cots的空间应用系统的测试

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474085

Sara Carbonara, A. Firrincieli, M. Reorda, Jan-Gerd Mess

引用次数: 4

Effective Control Flow Integrity Checks for Intrusion Detection 有效的入侵检测控制流完整性检查

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474130

A. Chaudhari, J. Abraham

引用次数: 3