Development flow of on-line Software Test Libraries for asynchronous processor cores

Asynchronous design style is quite appealing from various perspectives. In particular, several studies confirmed the reliability of asynchronous circuits in harsh environments, being capable to better tolerate power supply and temperature variations with respect to their synchronous counterparts. However, despite these advantages and many others, their applicability (especially in safety-critical scenarios) is quite limited today. Additionally, commercial EDA tools can be hardly used for asynchronous designs; hence, designers are discouraged of using such approaches for their applications. Notably, devices deployed for safety-critical applications must satisfy stringent requirements in order to guarantee the highest level of functional safety. Commonly, on-line testing mechanisms are necessary to achieve standards compliance. Such mechanisms undergo a validation process to assess their effectiveness, fault injection campaigns being the most commonly used. For doing so, designers exploit commercial EDA tools, intended to certificate standard compliance. In this paper, a methodology for the validation of Software Test Libraries (STLs) targeting on-line testing of asynchronous processor cores is proposed. The methodology is based exclusively on commercial tools, currently used in industry for functional safety analysis.