2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)最新文献_第6页

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks 使用CMOS FD-SOI而不是CMOS本体来增强ic抵御激光攻击的情况

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474230

J. Dutertre, V. Beroulle, P. Candelier, Louis-Barthelemy Faber, M. Flottes, P. Gendrier, D. Hély, R. Leveugle, P. Maistri, G. D. Natale, Athanasios Papadimitriou, B. Rouzeyre

引用次数: 4

Self-Stabilizing High-Speed Communication in Multi-Synchronous GALS Architectures 多同步GALS体系结构中的自稳定高速通信

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474221

Martin Perner, U. Schmid

引用次数: 0

A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays 用于单/多级交叉点RRAM阵列的低成本软容错读电路

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474076

Hossein Bardareh, Amir M. Hajisadeghi, H. Zarandi

引用次数: 4

Performances VS Reliability: how to exploit Approximate Computing for Safety-Critical applications 性能VS可靠性:如何在安全关键应用中利用近似计算

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474122

G. Rodrigues, F. Kastensmidt, V. Pouget, A. Bosio

引用次数: 8

[Title page] (标题页)

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/iolts.2018.8474102

引用次数: 0

Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory 提高相变存储器可靠性和良率的自适应ECC技术

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474118

Shyue-Kung Lu, Hui-Ping Li, K. Miyase

引用次数: 1

On the Effect of Aging in Detecting Hardware Trojan Horses with Template Analysis 老化对模板分析检测硬件木马的影响

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474089

Naghmeh Karimi, J. Danger, S. Guilley

{"title":"On the Effect of Aging in Detecting Hardware Trojan Horses with Template Analysis","authors":"Naghmeh Karimi, J. Danger, S. Guilley","doi":"10.1109/IOLTS.2018.8474089","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474089","url":null,"abstract":"With the outsourcing of design flow, ensuring the security and trustworthiness of integrated circuits has become more challenging. Potential malicious modification of circuits, so-called Hardware Trojans Horses (HTH), has emerged as a major security threat. When triggered, the HTH delivers its payload resulting in denial of service, decreasing the device performance, or leaking sensitive information. Deploying VLSI testing schemes to detect HTH may fail in most cases as HTH are designed such that they are rarely activated. Side-channel analysis schemes have a higher detection coverage. The template analysis is the most powerful side-channel tool from an information theoretic point of view. In this paper, we focus on the template analysis used for detecting HTH in cryptographic devices, and study the effect of device aging on the success of these HTH detection schemes. Due to aging, electrical specifications of transistors, and in turn the power signatures used by template schemes change over time. We focus on Negative-Bias Temperature Instability and Hot-Carrier Injection aging mechanisms. We use the PRESENT cipher as a target, and mount several template attacks at different aging times on target devices and a genuine device used as reference. We deduce the authenticity of the target devices based on the attack success rates obtained by template analysis. Our results show that aging makes template-based HTH detection easier as it needs less traces in old devices compared to the new one (137 traces for a 20-week old device versus 195 traces for a new one).","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117065015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping 基于FPGA原型的ASIC功率、温度和老化监测系统仿真

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474284

A. Listl, Daniel Mueller-Gritschneder, F. Kluge, Ulf Schlichtmann

{"title":"Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping","authors":"A. Listl, Daniel Mueller-Gritschneder, F. Kluge, Ulf Schlichtmann","doi":"10.1109/IOLTS.2018.8474284","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474284","url":null,"abstract":"Technology scaling has enabled the fabrication of Multi-Processor Systems-on-Chips (MPSoCs), which satisfy the ever growing demand for performance, while continuously reducing the chip size. Thus, scaling has also led to new challenges such as increasing power densities, which critically influence the chip temperatures and accelerate device degradation due to aging. Runtime power management can be utilized to counter these reliability threats to increase the lifetime of a system. For the development of runtime power management strategies monitoring data for power, temperature and aging is required. In this paper we propose a real-time power, temperature and aging monitor system (eTAPMon) for FPGA prototypes of MPSoCs. The monitor system emulates data characterized from the target ASIC design. The emulation approach models the behavior of ASIC power monitors based on an instruction-level energy model, temperature monitors based on a linear regression model obtained from thermal offline simulations and aging monitors based on a critical path model to compute the decreasing timing margin due to aging. An accelerated aging emulation is possible to predict aged ASIC behavior. Hence, this FPGA emulation enables the early evaluation of runtime power management strategies.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115169187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Error Resilient Neuromorphic Networks Using Checker Neurons 使用检查神经元的错误弹性神经形态网络

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474075

Sujay Pandey, Suvadeep Banerjee, A. Chatterjee

引用次数: 7

Cross-Layer Control Adaptation for Autonomous System Resilience 自治系统弹性的跨层控制自适应

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) Pub Date : 2018-07-01 DOI: 10.1109/IOLTS.2018.8474159

Md Imran Momtaz, Suvadeep Banerjee, Sujay Pandey, J. Abraham, A. Chatterjee

{"title":"Cross-Layer Control Adaptation for Autonomous System Resilience","authors":"Md Imran Momtaz, Suvadeep Banerjee, Sujay Pandey, J. Abraham, A. Chatterjee","doi":"10.1109/IOLTS.2018.8474159","DOIUrl":"https://doi.org/10.1109/IOLTS.2018.8474159","url":null,"abstract":"The last decade has seen tremendous advances in the transformation of ubiquitous control, computing and communication platforms that are anytime, anywhere. These platforms allow humans to interact with machines through sensing, control and actuation functions in ways not imaginable a few decades ago. While robust control techniques aim to maintain autonomous system performance in the presence of bounded modeling errors, they are not designed to manage large multi- parameter variations and internal component failures that are inevitable during lengthy periods of field deployment. To address the trustworthiness of autonomous systems in the field, we propose a cross-layer error resilience approach in which errors are detected and corrected at appropriate levels of the design (hardware-through software) with the objective of minimizing the latency of error recovery while maintaining high failure coverage. At the control processor level, soft errors in the digital control processor are considered. At the system level, sensor and actuator failures are analyzed. These impairments define the health of the system. A methodology for adapting the control procedure of the autonomous system to compensate for degraded system health is proposed. It is shown how this methodology can be applied to simple linear and nonlinear control systems to maintain system performance in the presence of internal component failures. Experimental results demonstrate the feasibility of the proposed methodology.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127565203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4