{"title":"Self-Stabilizing High-Speed Communication in Multi-Synchronous GALS Architectures","authors":"Martin Perner, U. Schmid","doi":"10.1109/IOLTS.2018.8474221","DOIUrl":null,"url":null,"abstract":"We describe a simple self-stabilizing point-to-point communication protocol for multi-synchronous GALS (globally asynchronous locally synchronous) systems. Its implementation is based on a ring buffer, which compensates for the clock deviations of sender and receiver. Read and write pointers separated by a suitable offset facilitate metastability-free operation without the need for synchronizers. We conduct a detailed analysis of the required buffer size and offset, which allows to tailor the protocol to given clock parameters like frequency bounds and synchronization precision. Simulation results obtained by means of a VHDL implementation of our approach prove its practical feasibility.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IOLTS.2018.8474221","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We describe a simple self-stabilizing point-to-point communication protocol for multi-synchronous GALS (globally asynchronous locally synchronous) systems. Its implementation is based on a ring buffer, which compensates for the clock deviations of sender and receiver. Read and write pointers separated by a suitable offset facilitate metastability-free operation without the need for synchronizers. We conduct a detailed analysis of the required buffer size and offset, which allows to tailor the protocol to given clock parameters like frequency bounds and synchronization precision. Simulation results obtained by means of a VHDL implementation of our approach prove its practical feasibility.