CMOS Characterization and Compact Modelling for Circuit Reliability Simulation

Abstract

With nowadays nanometer-CMOS technologies, time-zero and time dependent variability effects (like BTI, CHI, RTN, TDDB, EM, etc) have turned into an even more serious threat to the desired performance of analog and digital integrated circuits. Statistical characterization and modelling of these variability effects entail large testing times, which are typically prohibitive, and huge amounts of data, which are complex to post process. This paper describes novel characterization techniques that overcome these limitations, that is, they are capable of statistically testing nanometer CMOS devices with much shorter completion times. To properly handle the massive amounts of data from characterization, new extraction methods, described in this paper as well, have been developed. With these methods, an accurate variability-aware device model is completed, which can subsequently be used in reliability-aware circuit design methodologies.