Finding False Paths for Sequential Circuits Using Operations on ROBDDs

Performance of VLSI is, first of all, its high operation speed determined by a clock frequency. Developing of VLSI is oriented to maximal possible clock frequency under correct functioning. Clock frequency estimation is reduced to finding paths with maximal delays (critical paths) among logical components of VLSI. But some of the selected paths may be false. It means that the path has no impact on component functioning. It is necessary to fmd such paths in order to exclude them from consideration when we determine clock frequency. Detecting false paths may increase VLSI operation speed. The precise method of fmding false paths in a sequential circuit based on finding test pairs for non-robust path delay faults (PDFs) is developed. The length of a transfer sequence delivering the test pair from the initial internal state is not more the given value l. The method is based on applying operations on ROBDDs extracted from the combinational part of a sequential circuit. Experimental results illustrate the suggested method.