{"title":"容错混合临界系统的实时验证","authors":"Stefano Esposito, J. Sini, M. Violante","doi":"10.1109/IOLTS.2018.8474091","DOIUrl":null,"url":null,"abstract":"Modern avionics and space applications are characterized by increasing performance requirements. To satisfy such requirements, the use of commercial-off-the-shelf (COTS) multi-processor system-on-chips (MPSoCs) is a convenient solution. However, such systems are not developed for the avionic use case, therefore a validation approach is in order. In this paper, a validation approach is proposed for fault isolation, detection, and recovery mechanisms applied to mitigate fault effects in mixed-criticality systems. The approach is based on a combination of hardware-in-the-loop testing and fault injection techniques. Experimental results prove that the proposed approach does not interfere with the temporal behavior of the system under-test while allowing a realistic test of the software.","PeriodicalId":241735,"journal":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Real-Time Validation of Fault-Tolerant Mixed-Criticality Systems\",\"authors\":\"Stefano Esposito, J. Sini, M. Violante\",\"doi\":\"10.1109/IOLTS.2018.8474091\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Modern avionics and space applications are characterized by increasing performance requirements. To satisfy such requirements, the use of commercial-off-the-shelf (COTS) multi-processor system-on-chips (MPSoCs) is a convenient solution. However, such systems are not developed for the avionic use case, therefore a validation approach is in order. In this paper, a validation approach is proposed for fault isolation, detection, and recovery mechanisms applied to mitigate fault effects in mixed-criticality systems. The approach is based on a combination of hardware-in-the-loop testing and fault injection techniques. Experimental results prove that the proposed approach does not interfere with the temporal behavior of the system under-test while allowing a realistic test of the software.\",\"PeriodicalId\":241735,\"journal\":{\"name\":\"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IOLTS.2018.8474091\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IOLTS.2018.8474091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Real-Time Validation of Fault-Tolerant Mixed-Criticality Systems
Modern avionics and space applications are characterized by increasing performance requirements. To satisfy such requirements, the use of commercial-off-the-shelf (COTS) multi-processor system-on-chips (MPSoCs) is a convenient solution. However, such systems are not developed for the avionic use case, therefore a validation approach is in order. In this paper, a validation approach is proposed for fault isolation, detection, and recovery mechanisms applied to mitigate fault effects in mixed-criticality systems. The approach is based on a combination of hardware-in-the-loop testing and fault injection techniques. Experimental results prove that the proposed approach does not interfere with the temporal behavior of the system under-test while allowing a realistic test of the software.