Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop最新文献

{"title":"EIR pareto as a prioritization tool for factory improvements","authors":"S. Saha, Chiang Yang, B. Auches","doi":"10.1109/ASMC.1995.484402","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484402","url":null,"abstract":"This paper will describe a methodology to prioritize factory indicators using EIR (EDO Improvement Ratio). The purpose of the EIR methodology is to set priorities between and within improvement teams in order to optimize the allocation of limited factory resources (both people and $) without defocusing from the overall factory priority-Maximum number of Good dice. Historically, during a ramp of a factory with a new technology, there are four indicators that compete for the limited resources of the factory: equipment installation, output improvement, line yield and die yield. In the initial phase of the ramp, equipment installation tends to be a priority and as the installations are completed, die yield takes the top priority followed by the other indicators. In a dynamic situation, it is not always easy to set priorities of the different teams (installation, improvement, line yield, die yield) with changing parameters (run rates, defects, utilization, losses) especially when the same resources are shared between multiple indicators.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129745994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RTP installed base productivity improvement project","authors":"T. Speranza, D. Tomlinson","doi":"10.1109/ASMC.1995.484364","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484364","url":null,"abstract":"Summary form only given, as follows. Rapid Thermal Processing (RTP) has recently undergone widespread acceptance for a number VLSI applications. The industry's largest supplier installed base RTP equipment, AG Associates has experienced exponential growth in an effort to meet both the expanding market and increasingly diverse applications. SEMATECH, a consortium supported by the US government and consisting of some of the largest domestic manufacturers of microelectronic products, was approached mid 1993 by several of its members with concern about RTP productivity issues. SEMATECH organized an official project with interested member companies and partnered with AG Associates. The project worked to understand the needs of the RTP installed base and developed an improvement strategy which focused on both the technical problems and business practices highlighted by users. The strategy included a definition of performance metrics, supplier development program, reliability improvement program and development/evaluation of specific engineering upgrades. The project successfully concluded February, 1995. The authors discuss the dynamic relationship between SEMATECH, its member companies and AG Associates. A review of the project includes what worked well and yielded quantifiable results, what succeeded with intangible benefits as well as recommendations for future efforts. A number of project initiatives were strategic in nature with anticipated latent benefit. The projects original objective included assisting AG in becoming a world class supplier of semiconductor equipment.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130282830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Managing multi-chamber tool productivity","authors":"B. Auches, G. Grewal, P. Silverman","doi":"10.1109/ASMC.1995.484379","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484379","url":null,"abstract":"Multi-chamber tools have enabled significant technical breakthroughs in wafer processing in the last decade. Expenditures for these tools are increasing as a percentage of the total capital base. Fully one-third of the capital dollars invested in 0.4 /spl mu/m technology processing equipment will be spent on multi-chamber tools. These tools also present some special productivity problems, as a significant portion of the tool can fail to produce wafers while the remaining portions of the tool still are able to do so at a reduced run rate. Classical measures of tool availability and run rates are insufficient to account for reduced output when part of the tool is down. This paper presents measurements, operating scenarios and operating guidelines to maximize multi-chamber tool productivity in a volume manufacturing environment.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114350034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Defect sampling methodology: the development of an effective defect sampling strategy during the initial start-up phase of a 0.35 /spl mu/m fabrication facility","authors":"R. Cappel, R. Hilton, J. Lim","doi":"10.1109/ASMC.1995.484384","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484384","url":null,"abstract":"Summary form only given, as follows. This paper details the path taken to develop a sampling strategy for monitoring defects within an advanced fabrication facility. The objective of this program is to develop a sampling plan that will provide for efficient process monitoring and effective yield prediction. The sampling plan will incorporate a strategy for the percentage of lots, the number of wafers within each lot and the diagnostic model formulated by researchers at Carnegie Mellon University and the University of California at Berkeley, data collected during the start-up phase of the fabrication process will be used in conjunction with factors such as equipment capacity, cost-of-ownership details and minimization of cycle time contributions by inspections to develop an inspection strategy that will allow for a quick progression from process development to a higher yielding manufacturing process.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132126619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Manufacturing modeling and optimization","authors":"D. O'Ferrell","doi":"10.1109/ASMC.1995.484400","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484400","url":null,"abstract":"The purpose of this project was to model and optimize the personnel and equipment utilization in Siltec's Epitaxial manufacturing process. Previous attempts to model the behavior of the process through static models (linear programming and spreadsheets) had not attempted to explain any of the variability experienced in the process line. SIMAN was used to create a simple model to study the effects of crosstraining on productivity and cycle time. The model was validated using actual production data from Siltec's production line. The programming of the model was verified by comparing \"boundary values\" with expected behavior. The model was used to predict production volumes given various absence rates and crosstraining levels. Additional experiments investigated the effects of Kanban size, equipment failure rates, operator staffing levels, and equipment capacity increases on operator staffing requirements, production throughput and WIP, and cycle time. During periods of normal operator absence (10%), productivity is improved by about 10% and cycle time is improved by about 50% if all operators are fully crosstrained. During periods of high operator absence (20%), productivity is improved by about 30% and cycle time is improved by about 50% if all operators are fully crosstrained. In all cases, equipment utilization is improved with increased crosstraining. Additional experiments allowed determination of required headcount, equipment additions, and Kanban size for optimized production throughput, WIP, and cycle time. The general conclusion of this project is an affirmation of expected behavior. Increasing crosstraining will improve productivity, especially during periods of high operator absence. Increasing Kanban size will increase throughput minimally while increasing WIP and cycle time considerably. Moderate increases in capacity at bottlenecks will result in dramatic increases in throughput. The model has been and will continue to be used to make qualitative and quantitative decisions concerning headcount, resource allocation, and expansion plans.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"2000 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125728182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Sensorization in a photolithography coat process","authors":"M. McCaslin","doi":"10.1109/ASMC.1995.484363","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484363","url":null,"abstract":"The growth of automation and automatic data collection in the semiconductor industry is providing engineers and manufacturers with an unprecedented insight into their processes and is crucial in the trend toward higher quality and error free processing. Some of the immediate benefits of automation are real time monitoring of process conditions, reduction in equipment downtime due to qualification testing, real time Statistical Process Control (SPC), elimination of operator induced error in equipment measurements, and process risk reduction. These benefits and others were realized through the implementation of a real time temperature monitoring system on a photolithography coat track. The system provides full time temperature monitoring, automatic SPC data logging during actual process conditions, state driven control of track interlock to prevent out of limit processing and process data tracking for real time performance of wafer bake stations. The system was realized by implementing a C-based state logic program in the QNX Windows real time operating system to drive Keithley METRABUS hardware monitoring SVG 8600 coat tracks.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125566381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A logistical management system using calculated raw-process-time factors for production control","authors":"J. W. Holmes","doi":"10.1109/ASMC.1995.484353","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484353","url":null,"abstract":"In 1990, the IBM semiconductor manufacturing facility in Essex Junction, Vermont, fabricated two basic types of memory products in one of its fabricators with a \"first-in first-out\" (FIFO) system for tracking individual wafer lots. When additional products in different technologies came on line, a \"pull range system\" was used to divide wafer processing into 24-hour segments. These ranges consisted of one to ten operations that were scheduled for completion in one day. By early 1993, the number of different products being produced at this semiconductor manufacturing facility increased significantly, exceeding the ability of production operators to view and manage these pull ranges. This paper describes a logistical management system that uses a calculated raw-process-time factor to control product. The system, installed on the wafer processing line, focuses on a stock date and raw processing data to organize and prioritize all product lots into one system. The stock data describes when a particular product lot is due, while the raw processing time defines the amount of time required to process a lot from beginning to end. This system has helped to maintain fabricator serviceability ratings in the high 90% range and is available to all operators, especially those processing lots that require the most attention (those behind schedule). Data derived from the system describes wafer-lot priorities and the order in which the lots must be run. The system prioritizes all lots being processed for each operation, thereby enabling operators to simply \"run the top lot\".","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127183570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Practical issues in run by run process control","authors":"D. Boning, W. Moyne, T. Smith, J. Moyne, A. Hurwitz","doi":"10.1109/ASMC.1995.484371","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484371","url":null,"abstract":"Several works have described the implementation of systems for the run by run (RbR) control of semiconductor fabrication processes. In this paper, we consider algorithmic issues not often discussed arising out of our experience in the RbR control of chemical mechanical polishing (CMP). These issues include, first, limits on multiple input variables (machine settings). Such constraints must be implemented efficiently, and we compare a fast heuristic-based constraint method against a full optimization approach. Second, an input weight method enables the process engineer to manage which input parameters should be more readily modified and which should be changed less. Third, we have found that rounding off of suggested recipes before use on equipment (because of limited granularity in machine settings) can degrade the operational results compared to those ideally expected. We describe a heuristic that handles the quantization of input variables so as to improve the model based recipes suggested by the controller. This heuristic avoids the computational implication of a full integer optimization problem. Finally, we discuss methods for the selection of key controller parameters (e.g. the \"forgetting factor\" in an exponentially weighted moving average controller). Together, these and similar practical barriers must be understood and solved in order to have a usable run by run control strategy. These extensions to the MIT RbR algorithms have been implemented and successfully demonstrated in the control of CMP processes.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129266349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluating workcell layouts","authors":"D. Nehme, R. McKiddie","doi":"10.1109/ASMC.1995.484351","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484351","url":null,"abstract":"Traditionally, the tools of a wafer fab are laid out into \"farms\" where tools that perform similar functions are located in one area. With a given process flow and farm layout, estimating material-movement metrics like number of interbay moves and total wafer travel distance is relatively straightforward. This is because there is a one-to-one correspondence between type of processing (etch, photo, etc.) and a given \"farm\" area. However, in a workcell or mixed farm-workcell layout, there is no such correspondence because similar tools are often located in different areas of the fab. In addition, these distributed tools often support multiple processing steps. Thus, it is a challenge for analysts to evaluate material movement metrics with workcell layouts because of the difficulty in assigning processing steps to particular tools. We present a simple linear programming model that, given the process flows, the start rates, and a fab layout, quickly performs this assignment. The model assigns steps to individual tools or to specific bays with the objective of minimizing wafer travel subject to tool capacity constraints. In performing this analysis, the modeling logic takes into account the fact that a lot of wafers will leave the same tool that it entered. This creates dependencies among assignments of process steps to tools. Linear programming is well suited to handle these types of dependencies. The model is intended for quick evaluations of layouts or given an existing layout, for assigning a processing flow to actual tools. In this paper we give an intuitive explanation of the model, and describe how we used it to evaluate the effect of different workcell designs on material movement.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121170022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Defect characterisation and reduction on a multi-chamber inter layer dielectric (ILD) tool","authors":"B. Prendergast, P. Hudson","doi":"10.1109/ASMC.1995.484407","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484407","url":null,"abstract":"Due to the decreasing geometry and increased production complexity in the Semiconductor industry, particle defects have become more critical in regard to wafer yield parameters. Current cleanroom technology success leads to contamination being attributed mainly to equipment operation. One of the key mechanisms is wearout of equipment parts. This paper discusses the techniques applied at Fab 10, Intel's European Semiconductor Manufacturing site and the success of correlating machine components wearout to metrology measurements. In 1 micron technology days, one could visually inspect machine components during preventive maintenance and make a \"judgment call\" on replacement. However, risks are too great in sub-micron technology where a flake from a worn-out part can cost several die and contaminate downstream tools. In an effort to put more science into the changeout frequency of parts, removing subjectivity, a Noran 'Voyager 2100' Microanalysis system on an Amray 2030L FESEM was used to collect and analyze the X-rays from both defects on blank oxide wafers and machine parts. A background baseline of new multi-chamber ILD Chemical Vapour Deposition (CVD) machines was initially performed, which corresponded to normal station monitor defect counts. When defect monitors on a particular machine trend upwards, further monitors were performed. In tandem, a basic description of machine components was obtained from the vendor for approved materials. Where we did not have specific composition of suspect parts, the suspect part would be changed out and another Energy Dispersive X-ray Spectroscopy (EDX) monitor performed. We were able to obtain spectra of submicron defects on blanket oxide wafers which were held in a catalog and compared to analysis results of machine parts such as o-ring wearout of chamber doors, showerhead wearout and quality of graphite components. The information allowed us to set realistic changeout frequency of parts before they became a problem. The EDX analysis was backed up by inline metrology measurements on product. The success of this led to EDX on a new inline system being the standard test before the ILD process tool was vented up for troubleshooting. From the spectra information library, a response flow checklist (RFC) was written, which is now used as a standard method of troubleshooting Out Of Control (OOCs) particle situations. This is also the standard test performed when upgrades/new parts are being qualified in our tools.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131520419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}