Proceedings 37th Design Automation Conference最新文献_第10页

Run-time voltage hopping for low-power real-time systems 低功耗实时系统的运行时电压跳变

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337785

Seongsoo Lee, T. Sakurai

引用次数: 257

Synthesis of application-specific memories for power optimization in embedded systems 嵌入式系统电源优化专用存储器的合成

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337424

L. Benini, A. Macii, E. Macii, M. Poncino

引用次数: 34

Interconnect testing in cluster-based FPGA architectures 基于集群的FPGA架构互连测试

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337310

I. Harris, R. Tessier

引用次数: 47

Projection frameworks for model reduction of weakly nonlinear systems 弱非线性系统模型约简的投影框架

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337380

J. Phillips

引用次数: 140

Synthesis-for-testability of controller-datapath pairs that use gated clocks 使用门控时钟的控制器-数据路径对的可测试性综合

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337595

M. Nourani, J. Carletta, C. Papachristou

引用次数: 4

Routing tree construction under fixed buffer locations 在固定缓冲区位置下构建路由树

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337502

J. Cong, Xin Yuan

{"title":"Routing tree construction under fixed buffer locations","authors":"J. Cong, Xin Yuan","doi":"10.1145/337292.337502","DOIUrl":"https://doi.org/10.1145/337292.337502","url":null,"abstract":"Modern high performance design requires using a large number of buffers. In practice, buffers are organized into buffer blocks and planned in the early stages of design process [1]. Thus, the locations of buffer blocks are usually fixed prior to routing tree construction. In this paper we present the first algorithm for simultaneous routing tree construction and buffer insertion for multiple-pin nets under fixed buffer locations. Given a source and n sinks of a net, the required arrival time associated with each sink, and m buffers with fixed locations, our algorithm can construct a routing tree for this net with possible insertion of buffers at given locations such that the required arrival time at the source is maximized. Experimental results show that our algorithm is efficient to handle fixed buffer location constraints and can also be used for routing tree construction without buffer insertion. Moreover, it can handle obstacles and congestion which will benefit its adaption in a global router. Compared to the well-known BA-tree algorithm [2] followed by a post-processing step for handling fixed buffer location constraints, our algorithm outperforms it by up to 46% in terms of delay while using comparative wirelength.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133228259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 52

A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers 数字通信收发器混合信号前端的高效高级数据流仿真方法

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337535

G. Vandersteen, P. Wambacq, Y. Rolain, P. Dobrovolný, S. Donnay, M. Engels, I. Bolsens

引用次数: 23

Boolean satisfiability in electronic design automation 电子设计自动化中的布尔可满足性

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337611

Joao Marques-Silva, K. Sakallah

{"title":"Boolean satisfiability in electronic design automation","authors":"Joao Marques-Silva, K. Sakallah","doi":"10.1145/337292.337611","DOIUrl":"https://doi.org/10.1145/337292.337611","url":null,"abstract":"Boolean Satisfiability (SAT) is often used as the underlying model for a significant and increasing number of applications in Electronic Design Automation (EDA) as well as in many other fields of Computer Science and Engineering. In recent years, new and efficient algorithms for SAT have been developed, allowing much larger problem instances to be solved. SAT “packages” are currently expected to have an impact on EDA applications similar to that of BDD packages since their introduction more than a decade ago. This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem. Specifically, we highlight the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation, among others. In addition, we provide an overview of the algorithmic techniques commonly used for solving SAT, including those that have seen widespread use in specific EDA applications. We categorize these algorithmic techniques, indicating which have been shown to be best suited for which tasks.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123286439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 134

Communication architecture tuners: a methodology for the design of high-performance communication architectures for system-on-chips 通信架构调谐器:一种用于设计片上系统的高性能通信架构的方法

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337561

K. Lahiri, A. Raghunathan, G. Lakshminarayana, S. Dey

{"title":"Communication architecture tuners: a methodology for the design of high-performance communication architectures for system-on-chips","authors":"K. Lahiri, A. Raghunathan, G. Lakshminarayana, S. Dey","doi":"10.1145/337292.337561","DOIUrl":"https://doi.org/10.1145/337292.337561","url":null,"abstract":"In this chapter, we present a general methodology for the design of custom system-on-chip communication architectures. Our technique is based on the addition of a layer of circuitry, called the Communication Architecture Tuner (CAT), around any existing communication architecture topology. The added layer enhances the ability of the system to adapt to changing communication needs of its constituent components. For example, more critical data may be handled differently, leading to lower communication latencies. The CAT monitors the internal state and communication transactions of each component, and “predicts” the relative importance of each communication transaction in terms of its potential impact on different system-level performance metrics. It then configures the protocol parameters of the underlying communication architecture (e.g., priorities, DMA modes,etc.) to best suit the system's changing communication needs.\u0000We illustrate issues and tradeoffs involved in the design of CAT-based communication architectures, and present algorithms to automate the key steps. Experimental results indicate that performance metrics (e.g. number of missed deadlines, average processing time) for systems with CAT-based communication architectures are significantly (sometimes, over an order of magnitude) better than those with conventional communication architectures.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116322672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 54

Modeling and simulation of real defects using fuzzy logic 用模糊逻辑对真实缺陷进行建模与仿真

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337601

A. Attarha, M. Nourani, C. Lucas

引用次数: 6