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Proceedings 37th Design Automation Conference最新文献

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Fast post-placement rewiring using easily detectable functional symmetries 使用易于检测的功能对称性快速放置后重新布线
Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1109/DAC.2000.855320
C. Chang, Chung-Kuan Cheng, P. Suaris, M. Marek-Sadowska
{"title":"Fast post-placement rewiring using easily detectable functional symmetries","authors":"C. Chang, Chung-Kuan Cheng, P. Suaris, M. Marek-Sadowska","doi":"10.1109/DAC.2000.855320","DOIUrl":"https://doi.org/10.1109/DAC.2000.855320","url":null,"abstract":"Timing convergence problem arises when the estimations made during logic synthesis can not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A linear time algorithm is proposed to detect functional symmetries in the Boolean network and is used as the basis for rewiring. Integration with an existing gate sizing algorithm further proves the effectiveness of our technique. Experimental results are very promising.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121122118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Forensic engineering techniques for VLSI CAD tools VLSI CAD工具的取证工程技术
Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337584
D. Kirovski, David T. Liu, J. Wong, M. Potkonjak
{"title":"Forensic engineering techniques for VLSI CAD tools","authors":"D. Kirovski, David T. Liu, J. Wong, M. Potkonjak","doi":"10.1145/337292.337584","DOIUrl":"https://doi.org/10.1145/337292.337584","url":null,"abstract":"The proliferation of the Internet has affected the business model of almost all semiconductor and VLSI CAD companies that rely on intellectual property (IP) as their main source of revenues. The fact that IP has become more accessible and easily transferable, has influenced the emergence of copyright infringement as one of the most common obstructions to e-commerce of IP.\u0000In this paper, we propose a generic forensic engineering technique that addresses a number of copyright infringement scenarios. Given a solution <italic>S<subscrpt>P</subscrpt></italic> to a particular optimization problem instance <italic>P</italic> and a finite set of algorithms <italic>A</italic> applicable to <italic>P</italic>, the goal is to identify with a certain degree of confidence the algorithm <italic>A<subscrpt>i</subscrpt></italic> which has been applied to <italic>P</italic> in order to obtain <italic>S<subscrpt>P</subscrpt></italic>. We have applied forensic analysis principles to two problem instances commonly encountered in VLSI CAD: graph coloring and boolean satisfiability. We have demonstrated that solutions produced by strategically different algorithms can be associated with their corresponding algorithms with high accuracy.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114441429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Code compression for low power embedded system design 低功耗嵌入式系统的代码压缩设计
Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337423
H. Lekatsas, J. Henkel, W. Wolf
{"title":"Code compression for low power embedded system design","authors":"H. Lekatsas, J. Henkel, W. Wolf","doi":"10.1145/337292.337423","DOIUrl":"https://doi.org/10.1145/337292.337423","url":null,"abstract":"We propose instruction code compression as an efficient method for reducing power on an embedded system. Our approach is the first one to measure and optimize the power consumption of a complete SOC (System--On--a--Chip) comprising a CPU, instruction cache, data cache, main memory, data buses and address bus through code compression. We compare the pre-cache architecture (decompressor between main memory and cache) to a novel post-cache architecture (decompressor between cache and CPU). Our simulations and synthesis results show that our methodology results in large energy savings between 22% and 82% compared to the same system without code compression. Furthermore, we demonstrate that power savings come with reduced chip area and the same or even improved performance.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121907511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 146
Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction 具有多周期功能单元、异常和分支预测的超标量微处理器的正式验证
Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337331
M. Velev, R. Bryant
{"title":"Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction","authors":"M. Velev, R. Bryant","doi":"10.1145/337292.337331","DOIUrl":"https://doi.org/10.1145/337292.337331","url":null,"abstract":"We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors to be applicable to designs where the functional units and memories have multicycle and possibly arbitrary latency. We also show ways to incorporate exceptions and branch prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted Functions [4][5]. We study the modeling of the above features in different versions of dual-issue superscalar processors.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130528019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 114
Schedulability-driven performance analysis of multiple mode embedded real-time systems 多模式嵌入式实时系统可调度性驱动性能分析
Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337556
Youngsoo Shin, Daehong Kim, Kiyoung Choi
{"title":"Schedulability-driven performance analysis of multiple mode embedded real-time systems","authors":"Youngsoo Shin, Daehong Kim, Kiyoung Choi","doi":"10.1145/337292.337556","DOIUrl":"https://doi.org/10.1145/337292.337556","url":null,"abstract":"Providing multiple modes to support dynamically changing environments, standards, and new services is prevalent in embedded systems, especially in mobile radio systems. Because such a system frequently contains time-constrained tasks, it is important to analyze the temporal requirements as well as the functional correctness. This paper presents a method to analyze temporal requirements imposed on an embedded real-time system supporting multiple modes. While most performance analysis methods focus only on testing the feasibility of a task or a system, our method goes further by addressing the problem of locating hot spots of a system thereby helping the designer to choose among alternative designs or architectures. We formally define the analysis problem and show that it is very unlikely to be solved efficiently. We present a heuristic algorithm, which is accurate and fast enough to be used in iterative processes in system-level analysis and design. The analysis problem is extended to accommodate probabilistic behavior exhibited by soft real-time tasks.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114764610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
To split or to conjoin: the question in image computation 分割或合并:图像计算中的问题
Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1109/DAC.2000.855270
In-Ho Moon, J. Kukula, Kavita Ravi, F. Somenzi
{"title":"To split or to conjoin: the question in image computation","authors":"In-Ho Moon, J. Kukula, Kavita Ravi, F. Somenzi","doi":"10.1109/DAC.2000.855270","DOIUrl":"https://doi.org/10.1109/DAC.2000.855270","url":null,"abstract":"Image computation is the key step in fixpoint computations that are extensively used in model checking. Two techniques have been used for this step: one based on conjunction of the terms of the transition relation, and the other based on recursive case splitting. We discuss when one technique outperforms the other, and consequently formulate a hybrid approach to image computation. Experimental results show that the hybrid algorithm is much more robust than the “pure” algorithms and outperforms both of them in most cases. Our findings also shed light on the remark of several researchers that splitting is especially effective in approximate reachability analysis.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128006514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 82
Wave-steering one-hot encoded FSMs 操波单热编码FSMs
Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337440
L. Macchiarulo, M. Marek-Sadowska
{"title":"Wave-steering one-hot encoded FSMs","authors":"L. Macchiarulo, M. Marek-Sadowska","doi":"10.1145/337292.337440","DOIUrl":"https://doi.org/10.1145/337292.337440","url":null,"abstract":"In this paper we address the problem of pipelining FSMs by extending wave-steering scheme from combinational to sequential realm. A unified approach employs direct mapping of State Transition Graph into a circuit realization. Experimental result on MCNC benchmarks show performance improvement of 2 to 4 times at the cost of an average area increase of 2.9 times.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125657880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Maze routing with buffer insertion and wiresizing 带缓冲区插入和布线的迷宫路由
Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1109/DAC.2000.855339
Minghorng Lai, Martin D. F. Wong
{"title":"Maze routing with buffer insertion and wiresizing","authors":"Minghorng Lai, Martin D. F. Wong","doi":"10.1109/DAC.2000.855339","DOIUrl":"https://doi.org/10.1109/DAC.2000.855339","url":null,"abstract":"We propose an elegant formulation of the Maze Routing with Buffer Insertion and Wiresizing pr oblem as a graph-the oretic shortest path problem. This formulation provides time and space performance improvements over previously proposed dynamic-programming based techniques. R outing c onstr aints such as wiring obstacles and restrictions on buffer locations and types are easily inc orporated in the formulation. Furthermore, efficient softwar e routines solving shortest path problems in existing graph applic ation libraries can be applied. We construct a BP-Graph such that the length of every path in this graph is e qual to the Elmore delay. Therefore, finding the minimum Elmore delay path becomes a finite shortest path problem. The buffer choices and insertion locations are repr esente d as the vertices in the BP-Graph. The inter connect wir es are sized by constructing a look-up table for buffer-to-buffer wir esizing solutions. We also provide a technique that is able to tremendously improve the runtime. Experiments show improvements over previously proposed methods.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132592236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Memory aware compilation through accurate timing extraction 内存感知编译通过精确的定时提取
Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337428
P. Grun, N. Dutt, A. Nicolau
{"title":"Memory aware compilation through accurate timing extraction","authors":"P. Grun, N. Dutt, A. Nicolau","doi":"10.1145/337292.337428","DOIUrl":"https://doi.org/10.1145/337292.337428","url":null,"abstract":"Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this bottleneck. However, such features can not be efficiently exploited in processor-based embedded systems without memory-aware compiler support. We describe a memory-aware compiler approach that exploits such efficient memory access modes by extracting accurate timing information, allowing the compiler's scheduler to perform global code reordering to better hide the latency of memory operations. Our memory-aware compiler scheduled several benchmarks on the TI C6201 processor architecture interfaced with a 2-bank synchronous DRAM and generated average improvements of 24% over the best possible schedule using a traditional (memory-transparent) optimizing compiler, demonstrating the utility of our memory-aware compilation approach.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133231453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system 用于可重构多处理器系统的WDMA无源光总线的高级模型
Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337395
V. Boros, A. Rakić, S. Parameswaran
{"title":"High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system","authors":"V. Boros, A. Rakić, S. Parameswaran","doi":"10.1145/337292.337395","DOIUrl":"https://doi.org/10.1145/337292.337395","url":null,"abstract":"We describe the first iteration of a comprehensive model with which we can investigate the practical limits on optical bus bandwidth and number of bus processing modules for given signal power. The selection algorithm will ultimately allow programmable evaluation of system parameters bus bandwidth, optical power budget, electrical power budget, number of modules and space consumption for an optimal design that is suited to on-the-fly system reconfiguration.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115013075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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