Proceedings 37th Design Automation Conference最新文献_第2页

Practical iterated fill synthesis for CMP uniformity CMP均匀性的实用迭代填充合成

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337610

Yu Chen, A. Kahng, G. Robins, A. Zelikovsky

引用次数: 51

Closing the gap between analog and digital 缩小模拟和数字之间的差距

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337775

K. Saab, Naim Ben-Hamida, B. Kaminska

引用次数: 1

On lower bounds for scheduling problems in high-level synthesis 高级综合中调度问题的下界

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337573

M. Narasimhan, J. Ramanujam

引用次数: 5

A codesign virtual machine for hierarchical, balanced hardware/software system modeling 一种用于分层、平衡硬件/软件系统建模的协同设计虚拟机

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337506

J. M. Paul, S. Peffers, D. E. Thomas

引用次数: 9

METRICS: a system architecture for design process optimization METRICS:用于设计过程优化的系统架构

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337745

S. Fenstermaker, David George, A. Kahng, S. Mantik, Bart Thielges

引用次数: 37

YAPI: application modeling for signal processing systems 用于信号处理系统的应用程序建模

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337511

E. Kock, W. Smits, P. V. D. Wolf, J. Brunel, W. Kruijtzer, P. Lieverse, K. Vissers, G. Essink

引用次数: 369

A design of and design tools for a novel quantum dot based microprocessor 一种新型量子点微处理器的设计与设计工具

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337398

M. Niemier, Michael Kontz, P. Kogge

引用次数: 81

Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability 基于模型的假人特征定位用于氧化物化学机械抛光可制造性

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337609

Ruiqi Tian, Martin D. F. Wong, R. Boone

{"title":"Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability","authors":"Ruiqi Tian, Martin D. F. Wong, R. Boone","doi":"10.1145/337292.337609","DOIUrl":"https://doi.org/10.1145/337292.337609","url":null,"abstract":"Chemical-mechanical polishing (CMP) is an enabling technique used in deep-submicron VLSI manufacturing to achieve uniformity in long range oxide planarization [1]. Post-CMP oxide topography is highly related to local spatial pattern density in layout. To change local pattern density, and thus ensure post-CMP planarization, dummy features are placed in layout. Based on models that accurately describe the relation between local pattern density and post-CMP planarization [7; 5; 9], a two-step procedure of global density assignment followed by local insertion is proposed to solve the dummy feature placement problem in the fixed-dissection regime with both single-layer and multiple-layer considerations. Two experiments, conducted with real design data, gave excellent results by reducing post-CMP topography variation from 767Å to 152Å in the single-layer formulation and by avoiding cumulative effect in the multiple-layer formulation. The result from single-layer formulation compares very favorably both to the rule-based approach widely used in industry and to the algorithm in [3]. The multiple-layer formulation has no previously published work.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130392082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 121

Design of system-on-a-chip test access architectures under place-and-route and power constraints 片上系统测试存取架构在位置和路由及功率限制下的设计

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337531

K. Chakrabarty

引用次数: 92

Automatic test pattern generation for functional RTL circuits using assignment decision diagrams 使用分配决策图自动生成功能RTL电路的测试模式

Proceedings 37th Design Automation Conference Pub Date : 2000-06-01 DOI: 10.1145/337292.337309

Indradeep Ghosh, M. Fujita

{"title":"Automatic test pattern generation for functional RTL circuits using assignment decision diagrams","authors":"Indradeep Ghosh, M. Fujita","doi":"10.1145/337292.337309","DOIUrl":"https://doi.org/10.1145/337292.337309","url":null,"abstract":"In this paper, we present an algorithm for generating test patterns automatically from functional register transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level. To do this we utilize a data structure named assignment decision diagram which has been proposed previously in the field of high level synthesis. The advent of RTL synthesis tools have made functional RTL designs widely popular. This paper addresses the problem of test pattern generation directly at this level due to a number of advantages inherent at the RTL. Since the number of primitive elements at the RTL is usually lesser than the logic level, the problem size is reduced leading to a reduction in the test generation time over logic-level ATPG. A reduction in the number of backtracks can lead to improved fault coverage and reduced test application time over logic-level techniques. The test patterns thus generated can also be used to perform RTL-RTL and RTL-logic validation. The algorithm is very versatile and can tackle almost any type of single-clock design though performance varies according to the design style. It gracefully degrades to an inefficient logic-level ATPG algorithm if it is applied to a logic-level circuit. Experimental results demonstrate that over 1000 times reduction in test generation time can be achieved by this algorithm on certain types of RTL circuits without any compromise in fault coverage.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131300177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43