{"title":"Performance driven multi-level and multiway partitioning with retiming","authors":"J. Cong, S. Lim, Chang Wu","doi":"10.1145/337292.337418","DOIUrl":"https://doi.org/10.1145/337292.337418","url":null,"abstract":"In this paper, we study the performance driven multiw ay circuit partitioning problem with consideration of the significant difference of local and global interconnect delay induced by the partitioning. We develop an efficient algorithm HPM (Hierarc hicalP erformance driven Multi-level partitioning) that simultaneously considers cutsize and delay minimization with retiming. HPM builds a multi-lev el cluster hierarc hy and performs various refinement while gradually decomposing the clusters for simultaneous cutsize and delay minimization. We provide comprehensive experimental justification for each step involv ed in HPM and in-depth analysis of cutsize and delay tradeoff existing in the performance driven partitioning problem. HPM obtains (i) 7% to 23% better delay compared to the state-of-the-art cutsize driven hMetis [11] at the expense of 19% increase in cutsize, and (ii) 81% better cutsize compared to the state-of-the-art delay driven PRIME [2] at the expense of 6% increase in delay.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127668077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Somasekhar, Seung Hoon Choi, K. Roy, Y. Ye, V. De
{"title":"Dynamic noise analysis in precharge-evaluate circuits","authors":"D. Somasekhar, Seung Hoon Choi, K. Roy, Y. Ye, V. De","doi":"10.1145/337292.337406","DOIUrl":"https://doi.org/10.1145/337292.337406","url":null,"abstract":"A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of noise-injection in the circuit is cross-talk, a simple metric represented as voltage-time product can be used to quantify the dynamic noise-margin. This is verified by HSPICE simulation on DOMINO gates. A tool is also developed to obtain static and dynamic noise-margins at various points in the circuit. Dynamic noise-margins are translated into maximum allowable coupling capacitances between the pairs of nets for precharge-evaluate logic circuits. An accurate estimate of dynamic noise-margin and coupling coefficient bounds will allow improvement of the circuits in terms of robustness.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115947955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application-specific memory management for embedded systems using software-controlled caches","authors":"Derek Chiou, P. Jain, L. Rudolph, S. Devadas","doi":"10.1145/337292.337523","DOIUrl":"https://doi.org/10.1145/337292.337523","url":null,"abstract":"We propose a way to improve the performance of embedded processors running data-intensive applications by allowing software to allocate on-chip memory on an application-specific basis. On-chip memory in the form of cache can be made to act like scratch-pad memory via a novel hardware mechanism, which we call column caching. Column caching enables dynamic cache partitioning in software, by mapping data regions to a specified sets of cache “columns” or “ways.” When a region of memory is exclusively mapped to an equivalent sized partition of cache, column caching provides the same functionality and predictability as a dedicated scratchpad memory for time-critical parts of a real-time application. The ratio between scratchpad size and cache size can be easily and quickly varied for each application, or each task within an application. Thus, software has much finer software control of on-chip memory, providing the ability to dynamically tradeoff performance for on-chip memory.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127161483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Domino logic synthesis minimizing crosstalk","authors":"Ki-Wook Kim, U. Narayanan, S. Kang","doi":"10.1109/DAC.2000.855319","DOIUrl":"https://doi.org/10.1109/DAC.2000.855319","url":null,"abstract":"Based on the new concept of crosstalk immunity set (CIS), procedures to minimize capacitive cross-coupling effects are developed for domino logic circuit. The nets in a crosstalk immunity set are free from crosstalk effects for any combination of input vectors. New algorithms for CIS identification and minimization are proposed to maximize the chance of crosstalk minimization in routing step. Our routing algorithm augmented with CIS information searches for optimal solution to minimize maximum crosstalk the circuit would experience. Experimental results show that the reduction of maximum crosstalk is up to 30% with CIS-augmented routing.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125481187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power minimization using control generated clocks","authors":"M. S. Rao, S. Nandy","doi":"10.1145/337292.337781","DOIUrl":"https://doi.org/10.1145/337292.337781","url":null,"abstract":"In this paper we describe an area efficient power minimization scheme. “Control Generated Clocking” that saves significant amounts of power in datapath registers and clock drivers of sequential circuits. Power savings are achieved by making simple changes to the state machines controlling the datapath. These changes enable the control signals from the state machines themselves to be used as clocks for the datapath registers. Use of these control generated clocks makes the static timing analysis of designs implementing this scheme simpler when compared to techniques such as clock gating. This scheme preserves the cycle boundaries on which registers load data, thereby allowing reuse of functional test cases developed for the original circuit. In this paper we also describe timing requirements of a design in which this scheme has been implemented, cost-benefit aspects of this scheme and an algorithm for the automatic synthesis of control generated clocks. Results from application of this technique on a complex design are then discussed.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132332174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliable verification using symbolic simulation with scalar values","authors":"Chris Wilson, D. Dill","doi":"10.1145/337292.337336","DOIUrl":"https://doi.org/10.1145/337292.337336","url":null,"abstract":"This paper presents an algorithm for hardware verification that uses simulation and satisfiability checking techniques to determine the correctness of a symbolic test case on a circuit. The goal is to have coverage greater than that of random testing, but with the ease of use and predictability of directed testing. The user uses symbolic variables in simple directed tests to increase the input space that is explored. The algorithm, which is called quasi-symbolic simulation, simulates these tests using only scalar (0,1,X) values internally causing potentially conservative values to be generated at the outputs. Divide and conquer of the symbolic input space is used to resolve this conservativeness. In the best case, this method is as efficient as symbolic simulation using BDDs and, in the worst case, gives coverage and predictability at least as good as directed testing.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132741002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Verification of configurable processor cores","authors":"Marinés Puig-Medina, G. Ezer, P. Konas","doi":"10.1145/337292.337527","DOIUrl":"https://doi.org/10.1145/337292.337527","url":null,"abstract":"This paper presents a verification methodology for configurable processor cores. The simulation-based approach uses directed diagnostics and pseudo-random program generators both of which are tailored to specific processor instances. A configurable and extensible test-bench serves as the framework for the verification process and offers components necessary for the complete SOC verification. Coverage analysis provides an evaluation of how well a specific design has been exercised, of the breadth of the configuration space explored, and suggests improvements to the process. The results of the analysis show that our methodology achieves good verification coverage of the processor implementation.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131807859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"System design of active basestations based on dynamically reconfigurable hardware","authors":"A. Boulis, M. Srivastava","doi":"10.1145/337292.337557","DOIUrl":"https://doi.org/10.1145/337292.337557","url":null,"abstract":"Providing multiple modes to support dynamically changing environments, standards, and new services is prevalent in embedded systems, especially in mobile radio systems. Because such a system frequently contains time-constrained tasks, it is important to analyze the temporal requirements as well as the functional correctness. This paper presents a method to analyze temporal requirements imposed on an embedded real-time system supporting multiple modes. While most performance analysis methods focus only on testing the feasibility of a task or a system, our method goes further by addressing the problem of locating hot spots of a system thereby helping the designer to choose among alternative designs or architectures. We formally define the analysis problem and show that it is very unlikely to be solved efficiently. We present a heuristic algorithm, which is accurate and fast enough to be used in iterative processes in system-level analysis and design. The analysis problem is extended to accommodate probabilistic behavior exhibited by soft real-time tasks.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132245149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improved fault diagnosis in scan-based BIST via superposition","authors":"I. Bayraktaroglu, A. Orailoglu","doi":"10.1145/337292.337311","DOIUrl":"https://doi.org/10.1145/337292.337311","url":null,"abstract":"An improved approach for diagnosis of scan-based BIST designs is proposed. The enhancement in diagnosis is achieved by utilizing the superposition principle. Scan cells are partitioned pseudorandomly for observation and the ones provably fault free are removed from the potentially faulty list. Diagnostic resolution is improved by a novel application of the superposition principle, resulting in significant reductions in diagnosis time.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122613600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques","authors":"Chung-Yang Huang, K. Cheng","doi":"10.1109/DAC.2000.855289","DOIUrl":"https://doi.org/10.1109/DAC.2000.855289","url":null,"abstract":"We present a new approach to checking assertion properties for RTI, design verification. Our approach combines structural, word-level automatic test pattern generation (ATPG) and modular arithmetic constraint-solving techniques to solve the constraints imposed by the target assertion property. Our word-level ATPG and implication technique not only solves the constraints on the control logic, but also propagates the logic implications to the datapath. A novel arithmetic constraint solver based on modular number system is then employed to solve the remaining constraints in datapath. The advantages of the new method are threefold. First, the decision-making process of the word-level ATPG is confined to the selected control signals only. Therefore, the enumeration of enormous number of choices at the datapath signals is completely avoided. Second, our new implication translation techniques allow word-level logic implication being performed across the boundary of datapath and control logic, and therefore, efficiently cut down the ATPG search space. Third, our arithmetic constraint solver is based on modular instead of integral number system. It can thus avoid the false negative effect resulting from the bit-vector value modulation. A prototype system has been built which consists of an industrial front-end HDL parser, a property-to-constraint converter and the ATPG/arithmetic constraint-solving engine. The experimental results on some public benchmark and industrial circuits demonstrate the efficiency of our approach and its applicability to large industrial designs.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123043566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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