{"title":"用于可重构多处理器系统的WDMA无源光总线的高级模型","authors":"V. Boros, A. Rakić, S. Parameswaran","doi":"10.1145/337292.337395","DOIUrl":null,"url":null,"abstract":"We describe the first iteration of a comprehensive model with which we can investigate the practical limits on optical bus bandwidth and number of bus processing modules for given signal power. The selection algorithm will ultimately allow programmable evaluation of system parameters bus bandwidth, optical power budget, electrical power budget, number of modules and space consumption for an optimal design that is suited to on-the-fly system reconfiguration.","PeriodicalId":237114,"journal":{"name":"Proceedings 37th Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system\",\"authors\":\"V. Boros, A. Rakić, S. Parameswaran\",\"doi\":\"10.1145/337292.337395\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe the first iteration of a comprehensive model with which we can investigate the practical limits on optical bus bandwidth and number of bus processing modules for given signal power. The selection algorithm will ultimately allow programmable evaluation of system parameters bus bandwidth, optical power budget, electrical power budget, number of modules and space consumption for an optimal design that is suited to on-the-fly system reconfiguration.\",\"PeriodicalId\":237114,\"journal\":{\"name\":\"Proceedings 37th Design Automation Conference\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 37th Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/337292.337395\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 37th Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/337292.337395","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system
We describe the first iteration of a comprehensive model with which we can investigate the practical limits on optical bus bandwidth and number of bus processing modules for given signal power. The selection algorithm will ultimately allow programmable evaluation of system parameters bus bandwidth, optical power budget, electrical power budget, number of modules and space consumption for an optimal design that is suited to on-the-fly system reconfiguration.
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