Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction

M. Velev, R. Bryant
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引用次数: 114

Abstract

We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors to be applicable to designs where the functional units and memories have multicycle and possibly arbitrary latency. We also show ways to incorporate exceptions and branch prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted Functions [4][5]. We study the modeling of the above features in different versions of dual-issue superscalar processors.
具有多周期功能单元、异常和分支预测的超标量微处理器的正式验证
我们扩展了Burch和Dill冲洗技术[6],用于微处理器的正式验证,以适用于功能单元和存储器具有多周期和可能任意延迟的设计。我们还展示了通过利用具有未解释函数的正相等逻辑的属性来合并异常和分支预测的方法[4][5]。我们研究了在不同版本的双问题超标量处理器中上述特征的建模。
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