Modeling and simulation of real defects using fuzzy logic

Abstract

Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the traditional zero-resistance model is not sufficient. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate-level. Our method produces more realistic fault coverage compared to the conventional methods. The experimental results include the fault coverage and test pattern statistics for the ISCAS85 benchmarks.