Synthesis-for-testability of controller-datapath pairs that use gated clocks

Abstract

A method for high level synthesis-for-testability of controller-datapath pairs that use gated clocks is developed. It uses a register allocation technique that improves the observability of the controller through the datapath, and takes advantage of the unique testability properties of one-hot-encoded controllers. The resulting controller can be fully tested without isolating it from the system. Area, fault coverage, and power consumption are reported for three example circuits.