Proceedings of the 26th International Conference on Real-Time Networks and Systems最新文献

Formal approach for a verified implementation of Global EDF in Trampoline 在Trampoline中验证Global EDF实现的正式方法

Proceedings of the 26th International Conference on Real-Time Networks and Systems Pub Date : 2018-10-10 DOI: 10.1145/3273905.3273926

Khaoula Boukir, Jean-Luc Béchennec, A. Déplanche

引用次数: 1

Architecture-Aware Mapping and Scheduling of IMA partitions on Multicore platforms 多核平台上IMA分区的体系结构感知映射和调度

Proceedings of the 26th International Conference on Real-Time Networks and Systems Pub Date : 2018-10-10 DOI: 10.1145/3273905.3273914

Aishwarya Vasu, H. Ramaprasad

引用次数: 2

Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM 基于部分WCET分析和多保留时间STT-RAM的节能内存映射

Proceedings of the 26th International Conference on Real-Time Networks and Systems Pub Date : 2018-10-10 DOI: 10.1145/3273905.3273908

Rabab Bouziane, Erven Rohou, A. Gamatie

{"title":"Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM","authors":"Rabab Bouziane, Erven Rohou, A. Gamatie","doi":"10.1145/3273905.3273908","DOIUrl":"https://doi.org/10.1145/3273905.3273908","url":null,"abstract":"Energy-efficiency has become one major challenge in both embedded and high-performance computing. Different approaches have been investigated to solve the challenge, e.g., heterogeneous multicore, system runtime and device-level power management. This paper targets emerging nonvolatile memories (NVMs), through Spin-Transfer Torque RAM (STT-RAM), which inherently have quasi-null leakage. This enables to reduce the static power consumption, which tends to become dominant in modern systems. The usage of NVM in memory hierarchy comes however at the cost of expensive write operations in terms of latency and energy. In order to mitigate this detrimental feature, this paper leverages the notion of delta worst-case execution time (δ-WCET), which consists of partial WCET estimates. From program analysis, δ-WCETs are determined and used to safely allocate data to NVM memory banks with variable data retention times. The δ-WCET analysis computes the WCET between any two locations in a function code, i.e., between basic blocks or instructions. Our approach is validated on the Mälardalen benchmark suite and significant memory dynamic energy reductions (up to 80 %, and 66 % on average) are reported.","PeriodicalId":236964,"journal":{"name":"Proceedings of the 26th International Conference on Real-Time Networks and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129500888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol 硬件辅助时钟同步与IEEE 1588-2008精确时间协议

Proceedings of the 26th International Conference on Real-Time Networks and Systems Pub Date : 2018-10-10 DOI: 10.1145/3273905.3273920

Eleftherios Kyriakakis, J. Sparsø, Martin Schoeberl

{"title":"Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol","authors":"Eleftherios Kyriakakis, J. Sparsø, Martin Schoeberl","doi":"10.1145/3273905.3273920","DOIUrl":"https://doi.org/10.1145/3273905.3273920","url":null,"abstract":"Emerging technologies such as Fog Computing and Industrial Internet-of-Things have identified the IEEE 802.1Q amendment for Time-Sensitive Networking (TSN) as the standard for time-predictable networking. TSN is based on the IEEE 1588-2008 Precision Time Protocol (PTP) to provide a global notion of time over the local area network. Commonly, off-the-shelf systems implement the PTP in software where it has been shown to achieve microsecond accuracy. In the context of Fog Computing, it is hypothesized that future industrial systems will be equipped with FPGAs. Leveraging their inherent flexibility, the required PTP mechanisms can be implemented with minimal hardware usage and can achieve comparable synchronization results without the need for a PTP-capable transceiver. This paper investigates the practical challenges of implementing the PTP and proposes a hardware architecture that combines hardware-based timestamping with a rate adjustable clock design. The proposed architecture is integrated with the Patmos processor and evaluated on an experimental setup composed of two FPGA boards communicating through a commercial-off-the-shelf switch. The proposed implementation achieves sub-microsecond clock synchronization with a worst-case offset of 138 ns.","PeriodicalId":236964,"journal":{"name":"Proceedings of the 26th International Conference on Real-Time Networks and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130575960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

A Generalized Digraph Model for Expressing Dependencies 表示依赖关系的广义有向图模型

Proceedings of the 26th International Conference on Real-Time Networks and Systems Pub Date : 2018-10-10 DOI: 10.1145/3273905.3273918

Pascal Fradet, Xiaojie Guo, J. Monin, Sophie Quinton

{"title":"A Generalized Digraph Model for Expressing Dependencies","authors":"Pascal Fradet, Xiaojie Guo, J. Monin, Sophie Quinton","doi":"10.1145/3273905.3273918","DOIUrl":"https://doi.org/10.1145/3273905.3273918","url":null,"abstract":"In the context of computer assisted verification of schedulability analyses, very expressive task models are useful to factorize the correctness proofs of as many analyses as possible. The digraph task model seems a good candidate due to its powerful expressivity. Alas, its ability to capture dependencies between arrival and execution times of jobs of different tasks is very limited. We propose here a task model that generalizes the digraph model and its corresponding analysis for fixed-priority scheduling with limited preemption. A task may generate several types of jobs, each with its own worst-case execution time, priority, non-preemptable segments and maximum jitter. We present the correctness proof of the analysis in a way amenable to its formalization in the Coq proof assistant. Our objective (still in progress) is to formally certify the analysis for that general model such that the correctness proof of a more specific (standard or novel) analysis boils down to specifying and proving its translation into our model. Furthermore, expressing many different analyses in a common framework paves the way for formal comparisons.","PeriodicalId":236964,"journal":{"name":"Proceedings of the 26th International Conference on Real-Time Networks and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128836106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Algorithmic Complexity of Correctness Testing in MC-Scheduling mc调度中正确性测试的算法复杂度

Proceedings of the 26th International Conference on Real-Time Networks and Systems Pub Date : 2018-10-10 DOI: 10.1145/3273905.3273916

Rany Kahil, Dario Socci, P. Poplavko, S. Bensalem

{"title":"Algorithmic Complexity of Correctness Testing in MC-Scheduling","authors":"Rany Kahil, Dario Socci, P. Poplavko, S. Bensalem","doi":"10.1145/3273905.3273916","DOIUrl":"https://doi.org/10.1145/3273905.3273916","url":null,"abstract":"Previously, a lot of research has been done on scheduling a finite set of mixed criticality jobs with two levels of criticality on a single processor, which is also the subject of this work. It has been claimed that testing the correctness of solutions for this scheduling problem can be done in polynomial time. In this paper, we give a counter example to one of the lemmas used in that proof, reopening the question on whether the scheduling problem is in class NP. Taking into account our counter example, the authors who initially proved that correctness testing can be done in polynomial time published a fix to their proof. In the past, we proved that a previously existing correctness test is applicable for a quite general class of policies. From these results, for essentially the same class of policies, in this work we derive another correctness test, which transforms the policy to a new policy having a set of time-triggered tables, one for each criticality level. We show that the two policies are equivalent, in the sense that if one successfully schedules a jobs instance then so does the other. Thus the new transformed policy can be used for testing correctness of the original policy. We show that this correctness test has a lower algorithmic complexity than the existing test, due to the fact that the testing is done on only two static tables.","PeriodicalId":236964,"journal":{"name":"Proceedings of the 26th International Conference on Real-Time Networks and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121557952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Message scheduling to reduce AFDX jitter in a mixed NoC/AFDX architecture 在混合NoC/AFDX架构中减少AFDX抖动的消息调度

Proceedings of the 26th International Conference on Real-Time Networks and Systems Pub Date : 2018-10-10 DOI: 10.1145/3273905.3273929

Jérôme Ermont, S. Mouysset, Jean-Luc Scharbarg, C. Fraboul

{"title":"Message scheduling to reduce AFDX jitter in a mixed NoC/AFDX architecture","authors":"Jérôme Ermont, S. Mouysset, Jean-Luc Scharbarg, C. Fraboul","doi":"10.1145/3273905.3273929","DOIUrl":"https://doi.org/10.1145/3273905.3273929","url":null,"abstract":"Current avionics architecture are based on an avionics full duplex switched Ethernet network (AFDX) that interconnects end systems. Avionics functions exchange data through Virtual Links (VLs), which are static flows with bounded bandwidth. The jitter for each VL at AFDX entrance has to be less than 500 μs. This constraint is met, thanks to end system scheduling. The interconnection of many-cores by an AFDX backbone is envisioned for future avionics architecture. The principle is to distribute avionics functions on these many-cores. Many-cores are based on simple cores interconnected by a Network-on-Chip (NoC). The allocation of functions on the available cores as well as the transmission of flows on the NoC has to be performed in such a way that the jitter for each VL at AFDX entrance is still less than 500 μs. A first solution has been proposed, where each function manages the transmission of its VLs. The idea of this solution is to distribute functions on each many-core in order to minimize contentions for VLs which concern functions allocated on different many-cores. In this paper, we consider that VL transmissions are managed by a single task in each many-core. We propose to construct a scheduling table executed by this task using an Integer Linear Program. The access to the Ethernet interface is then only allowed to one VL leading to a significant reduction of the jitter.","PeriodicalId":236964,"journal":{"name":"Proceedings of the 26th International Conference on Real-Time Networks and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114544473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Trading Between Intra- and Inter-Task Cache Interference to Improve Schedulability 在任务内部和任务间缓存干扰之间进行交易以提高可调度性

Proceedings of the 26th International Conference on Real-Time Networks and Systems Pub Date : 2018-10-10 DOI: 10.1145/3273905.3273924

Syed Aftab Rashid, Geoffrey Nelissen, E. Tovar

{"title":"Trading Between Intra- and Inter-Task Cache Interference to Improve Schedulability","authors":"Syed Aftab Rashid, Geoffrey Nelissen, E. Tovar","doi":"10.1145/3273905.3273924","DOIUrl":"https://doi.org/10.1145/3273905.3273924","url":null,"abstract":"Caches help reduce the average execution time of tasks due to their fast operational speeds. However, caches may also severely degrade the timing predictability of the system due to intra- and inter-task cache interference. Intra-task cache interference occurs if the memory footprint of a task is larger than the allocated cache space or when two memory entries of that task are mapped to the same space in cache. Inter-task cache interference occurs when memory entries of two or more distinct tasks use the same cache space. State-of-the-art analysis focusing on bounding cache interference or reducing it by means of partitioning and by optimizing task layout in memory either focus on intra- or inter-task cache interference and do not exploit the fact that both intra- and inter-task cache interference can be interrelated. In this work, we show how one can model intra- and inter-task cache interference in a way that allows balancing their respective contribution to tasks worst-case response times. Since the placement of tasks in memory and their respective cache footprint determine the intra- and inter-task interference that tasks may suffer, we propose a technique based on cache coloring to improve task set schedulability. Experimental evaluations performed using Mälardalen benchmarks show that our approach results in up to 13% higher task set schedulability than state-of-the-art approaches.","PeriodicalId":236964,"journal":{"name":"Proceedings of the 26th International Conference on Real-Time Networks and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133911991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Elasticity of Workloads and Periods of Parallel Real-Time Tasks 并行实时任务的工作负载弹性和周期

Proceedings of the 26th International Conference on Real-Time Networks and Systems Pub Date : 2018-10-10 DOI: 10.1145/3273905.3273915

James Orr, C. Gill, Kunal Agrawal, Sanjoy Baruah, Christian Cianfarani, Phyllis Ang, C. Wong

{"title":"Elasticity of Workloads and Periods of Parallel Real-Time Tasks","authors":"James Orr, C. Gill, Kunal Agrawal, Sanjoy Baruah, Christian Cianfarani, Phyllis Ang, C. Wong","doi":"10.1145/3273905.3273915","DOIUrl":"https://doi.org/10.1145/3273905.3273915","url":null,"abstract":"The elastic task model allows sequential periodic real-time tasks, such as those found in multimedia players and adaptive control systems, to adjust their periods dynamically to manage quality of service or to accommodate other tasks. Recent theoretical advances show that parallel real-time tasks can adapt their periods similarly. This paper further extends the concept of elasticity of parallel real-time tasks, to allow them to adapt their computational workloads instead of their periods, such as when a real-time video processing application can improve image quality if it can do more computation within a given period. This paper also presents a new concurrency platform in which each parallel real-time task can adapt either its period or its workload, supporting heterogeneous forms of elasticity for different application needs. Empirical evaluations we have conducted (1) demonstrate the ability of this concurrency platform to enforce theoretical guarantees from both prior work and results developed in this paper, and (2) help to quantify and demonstrate tradeoffs between temporal and computational elasticity.","PeriodicalId":236964,"journal":{"name":"Proceedings of the 26th International Conference on Real-Time Networks and Systems","volume":"410 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133011472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems 多处理器双临界系统中低临界任务的优雅退化

Proceedings of the 26th International Conference on Real-Time Networks and Systems Pub Date : 2018-10-10 DOI: 10.1145/3273905.3273909

Lin Huang, I.-Hong Hou, S. Sapatnekar, Jiang Hu

{"title":"Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems","authors":"Lin Huang, I.-Hong Hou, S. Sapatnekar, Jiang Hu","doi":"10.1145/3273905.3273909","DOIUrl":"https://doi.org/10.1145/3273905.3273909","url":null,"abstract":"According to the conventional mixed-criticality (MC) system model, low-criticality tasks are completely discarded in high-criticality system mode. Allowing such loss of low-criticality tasks is controversial and not obviously necessary. We study how to achieve graceful degradation of low-criticality tasks by continuing their executions with imprecise computing or even precise computing if there is sufficient utilization slack. Schedulability conditions under this Variable-Precision Mixed-Criticality (VPMC) system model are investigated for partitioned scheduling and fpEDF-VD scheduling. It is found that the two scheduling methods in VMPC retain the same speedup factors as in conventional MC systems. We develop a precision optimization approach that maximizes precise computing of low-criticality tasks through 0-1 knapsack formulation. Experiments are performed through both software simulations and Linux prototyping with consideration of overhead. The results show that schedulability degradation caused by continuing low-criticality task execution is often very small. The proposed precision optimization can largely reduce computing errors compared to constantly executing low-criticality tasks with imprecise computing in high-criticality mode. The prototyping results indicate that partitioned scheduling in VPMC outperforms the latest work based on fluid model.","PeriodicalId":236964,"journal":{"name":"Proceedings of the 26th International Conference on Real-Time Networks and Systems","volume":"902 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132412165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11