2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献_第3页

Revisiting random access scan for effective enhancement of post-silicon observability 重新访问随机访问扫描，以有效增强后硅的可观测性

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046208

Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, B. Pandey, Virendra Singh

{"title":"Revisiting random access scan for effective enhancement of post-silicon observability","authors":"Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, B. Pandey, Virendra Singh","doi":"10.1109/IOLTS.2017.8046208","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046208","url":null,"abstract":"Due to tremendous growth in complexity of modern designs, bugs inevitably escape the pre-silicon verification stage. This has led to considerable increase in the time and effort dedicated to post-silicon validation. Debugging designs at postsilicon stage faces a severe bottleneck of limited observability of the internal states. This paper presents a methodology for post-silicon debug utilizing the special features of progressive random access scan (PRAS). The PRAS offers a read-out of nondestructive scan values which is the bottleneck in the process of debugging. The proposed methodology avoids the large overhead of additional resources for debugging as the DfT architecture is reused. PRAS provides a simultaneous solution to the problems of power, data volume and application time during testing at the cost of routing overhead. The PRAS based proposed architecture offers visibility of internal states in fewer clock cycles than traditional serial scan chain based debug methods. The proposed debug scheme offers reconfigurability which enables selective visibility of internal states of a certain portion of the design. Experimental results indicate the better performance of the proposed methodology as compared to the state restoration based observability enhancement techniques.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133301067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization 现场Fmax/Vmin跟踪能源效率和可靠性优化

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046240

I. Panades, E. Beigné, O. Billoint, Y. Thonnart

引用次数: 4

Controller augmentation and test point insertion at RTL for concurrent operational unit testing 控制器扩展和RTL测试点插入，用于并发操作单元测试

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046171

Toshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, Masayoshi Yoshimura

引用次数: 3

Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applications 软误差:能量受限ULP身体传感器网络应用中的可靠性挑战

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046222

H. Patel, B. Calhoun, R. Mann

引用次数: 4

Design flows for resilient energy-efficient systems 弹性节能系统的设计流程

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046243

M. Golanbari, M. Tahoori

引用次数: 0

NBTI/PBTI tolerant arbiter PUF circuits 耐NBTI/PBTI仲裁器PUF电路

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046201

Koyo Suzuki, K. Miura, K. Nakamae

{"title":"NBTI/PBTI tolerant arbiter PUF circuits","authors":"Koyo Suzuki, K. Miura, K. Nakamae","doi":"10.1109/IOLTS.2017.8046201","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046201","url":null,"abstract":"In this paper, we propose NBTI/PBTI (negative/positive bias temperature instability) tolerant arbiter PUF (physical unclonable function) circuits and evaluate its performance. The PUF is a technology for generating cryptographic keys and authenticating by utilizing physical characteristics, such as electronic delays, built in the devices when they were manufactured. It can perform encryption and authentication without directly holding the key, and has resistance to various eavesdropping attacks. On the other hand, its function may change due to aging degradation. To overcome this problem, we propose three types of NBTI/PBTI tolerant arbiter PUF circuits. These circuits cut off the stress voltage when it is in the standby mode. In the first type of circuit, cutoff features are added to all MOS transistors. In the second type of circuit, cutoff features are added to the MOS transistors which have a large influence on the delay. In the third type of the circuit, cutoff feature is added only to the primary input. Experiment by the SPICE simulation is carried out in order to evaluate our proposed circuits. The results show that there is a tradeoff between cost and error reduction rate, and the error rate is reduced to 1/8 in the best case.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121225047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Trojan circuits preventing and masking in sequential circuits 顺序电路中的木马电路预防和屏蔽

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046224

A. Matrosova, E. Mitrofanov, S. Ostanin, I. Kirienko

引用次数: 1

Reliability issues in RRAM ternary memories affected by variability and aging mechanisms 可变性和老化机制影响的随机存取存储器三元存储器可靠性问题

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046238

A. Rubio, M. Escudero, P. Pouyan

引用次数: 2

Assessment of the amplitude-duration criterion for SET/SEU robustness evaluation SET/SEU稳健性评价的振幅持续时间标准的评估

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046169

M. Andjelković, M. Krstic, R. Kraemer

{"title":"Assessment of the amplitude-duration criterion for SET/SEU robustness evaluation","authors":"M. Andjelković, M. Krstic, R. Kraemer","doi":"10.1109/IOLTS.2017.8046169","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046169","url":null,"abstract":"The relation between amplitude and duration of the current pulse induced by a high energy ionizing particle has been proposed as a criterion for evaluating the SET and SEU robustness of integrated circuits. This criterion has advantage over the widely accepted critical charge concept in the sense that it is less dependent on the current pulse shape. However, to the best of our knowledge, there is no known report on the impact of design and operating parameters on the amplitude-duration criterion. The need for extensive circuit or device simulations to derive the amplitude-duration curves under varying design and operating parameters makes this approach very time-consuming. In that regard, this work proposes a method to establish the amplitude-duration criterion, with a limited number of circuit simulations, as a rational function in terms of the sizing factors of target and load gates and supply voltage. Initial evaluation on a simple circuit composed of two inverters, designed in 130 nm bulk CMOS technology, has shown that the proposed method provides the accuracy comparable to SPICE simulations.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127001342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Deterministic network on chip for deploying real time applications on many-core processors 用于在多核处理器上部署实时应用程序的确定性片上网络

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046172

Stefano Esposito, M. Violante

引用次数: 1