2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献

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Reliability analysis of MTJ-based functional module for neuromorphic computing 基于mtj的神经形态计算功能模块可靠性分析
E. Vatajelu, L. Anghel
{"title":"Reliability analysis of MTJ-based functional module for neuromorphic computing","authors":"E. Vatajelu, L. Anghel","doi":"10.1109/IOLTS.2017.8046207","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046207","url":null,"abstract":"The power and reliability issues of today's memories limit the improvements attained by their implementation in scaled technology nodes. Several emergent memory technologies attempt to address the technical constraints of today's memories, amongst which, one of the most promising solutions is the Spin-Transfer-Torque Magnetic Random Access Memories (STT-MRAMs). One of the great advantages of the emerging memories is that they favor increasing system complexity and performance. New applications and computation paradigms, such as neuromorphic computing, unfeasible a few years back due to technological limitations, can take profit from this technology. Intensive research has been conducted recently related to magnetic device physics and its implementation as dedicated hardware for neuromorphic computing, however, little work has been conducted to evaluate the reliability of such circuits. In this paper we investigate the effect of meaningful MTJ reliability issues on the behavior of an MTJ-based Spiking Neural Network.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125033107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Energy-efficient and error-resilient iterative solvers for approximate computing 近似计算的节能和抗错迭代求解方法
A. Schöll, Claus Braun, H. Wunderlich
{"title":"Energy-efficient and error-resilient iterative solvers for approximate computing","authors":"A. Schöll, Claus Braun, H. Wunderlich","doi":"10.1109/IOLTS.2017.8046244","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046244","url":null,"abstract":"Iterative solvers like the Preconditioned Conjugate Gradient (PCG) method are widely-used in compute-intensive domains including science and engineering that often impose tight accuracy demands on computational results. At the same time, the error resilience of such solvers may change in the course of the iterations, which requires careful adaption of the induced approximation errors to reduce the energy demand while avoiding unacceptable results. A novel adaptive method is presented that enables iterative Preconditioned Conjugate Gradient (PCG) solvers on Approximate Computing hardware with high energy efficiency while still providing correct results. The method controls the underlying precision at runtime using a highly efficient fault tolerance technique that monitors the induced error and the quality of intermediate computational results.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130874159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On comparison of robust configurable FPGA encoders for dependable industrial communication systems 可靠工业通信系统中鲁棒可配置FPGA编码器的比较
P. Pfeifer, F. Hosseinzadeh, H. Vierhaus
{"title":"On comparison of robust configurable FPGA encoders for dependable industrial communication systems","authors":"P. Pfeifer, F. Hosseinzadeh, H. Vierhaus","doi":"10.1109/IOLTS.2017.8046217","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046217","url":null,"abstract":"Communication technologies have experienced an explosive development. Various short-distance communication systems have been used as a way of connecting embedded electronic systems in industrial applications. Test- and error detection or correction technologies have to meet new timing challenges and requirements in modern real-time and safety-critical systems, also set by Industry 4.0. Encoders using generator polynomials with linear-feedback shift registers (LFSRs) are the key parts of communication technologies, widely used in most of today's integrated as well as field systems. This paper presents a comparison of three basic ways of implementation of adaptive encoders configurable LFSRs using conventional configurable solutions, reconfigurable LUTs in SLICEMs in Xilinx FPGAs, and also encoders using standard Xilinx partial reconfiguration.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128265001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
EDA support for functional safety — How static and dynamic failure analysis can improve productivity in the assessment of functional safety EDA对功能安全的支持——静态和动态失效分析如何提高功能安全评估的生产率
D. Alexandrescu, A. Evans, M. Glorieux, I. Nofal
{"title":"EDA support for functional safety — How static and dynamic failure analysis can improve productivity in the assessment of functional safety","authors":"D. Alexandrescu, A. Evans, M. Glorieux, I. Nofal","doi":"10.1109/IOLTS.2017.8046210","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046210","url":null,"abstract":"Integrated circuits used in high-reliability applications must demonstrate low failure rates and high-levels of fault detection coverage. Safety Integrity Level (SIL) metrics indicated by the general IEC 61508 standard and the derived Automotive Safety Integrity Level (ASIL) specified by the ISO 26262 standard specify specific failure (FIT) rates and fault coverage metrics (e.g. SPFM and LFM) that must met. To demonstrate that an integrated circuit meets these expectations requires a combination of expert design analysis combined with fault injection (FI) simulations. During FI simulations, specific hardware faults (e.g. transients, stuck-at) are injected in specific nodes of the circuits (e.g. flip flops or logic gates). Designing an effective fault-injection platform is challenging, especially designing a platform that can be re used effectively across designs. We propose an architecture for a complete FI platform, easily integrated into a general-purpose design verification environment (DVE) that is implemented using UVM. The proposed fault simulation methodology is augmented using static analysis techniques based on fault propagation probability assessment and clustering approaches accelerating the fault simulation campaigns. The overall framework aims to: identify safety-threatening device features, provide objective failure metric and support design improvement efforts. We present a worked example where a 32-bit RISC V CPU has been subjected to an extensive static and dynamic failure analysis process, as a part of a standard-mandated functional safety assessment.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134038424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An effective functional safety infrastructure for system-on-chips 片上系统的有效功能安全基础设施
C. Eychenne, Y. Zorian
{"title":"An effective functional safety infrastructure for system-on-chips","authors":"C. Eychenne, Y. Zorian","doi":"10.1109/IOLTS.2017.8046235","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046235","url":null,"abstract":"With increasing use of electronic systems in vehicles for managing critical functionality, the requirements for safety in automotive chip architectures are becoming mandatory. Thus, automotive chips must provide functional safety capabilities in addition to the general functionality. Augmenting logic and memory BIST (Built-in Self-Test) solutions with new features is one of the options to facilitate safety at chip level. The augmented solution self-test the logic and memory at power-up/power-down and during mission mode to ensure that the chip is fault-free or react if it is faulty. In this paper, an effective infrastructure is presented which allow detection of faults for functional safety.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116499576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Advanced ECC solution for automotive SoCs 用于汽车soc的先进ECC解决方案
Hanna Shaheen, Gabriele Boschi, Gurgen Harutunyan, Y. Zorian
{"title":"Advanced ECC solution for automotive SoCs","authors":"Hanna Shaheen, Gabriele Boschi, Gurgen Harutunyan, Y. Zorian","doi":"10.1109/IOLTS.2017.8046237","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046237","url":null,"abstract":"The modern automotive industry has entered an era where the tendencies are towards increased automation and connectivity. With every new generation, the proportion of electronics-controlled systems in the vehicles is steadily growing. In parallel the safety and reliability requirements to automobiles are becoming more stringent thus requiring more sophisticated approaches. The problem is complicated by the fact that automotive has started to use cutting-edge technologies whose maturity might not be always at high level. Thus, there is a need to ensure not only low DPPM during production mode but also high reliability during mission mode. This paper presents an advanced Error Correcting Codes (ECC) solution which ensures high level of single-bit and multi-bit error detection and correction for memories operating in mission mode. This solution addresses the main requirements posed by automotive industry as well as successfully passed ISO 26262 certification with ASIL-D grade.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123026360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT 时序电路暂态故障脆弱性的SMT综合分析
Ghaith Bany Hamad, Ghaith Kazma, O. Mohamed, Y. Savaria
{"title":"Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT","authors":"Ghaith Bany Hamad, Ghaith Kazma, O. Mohamed, Y. Savaria","doi":"10.1109/IOLTS.2017.8046195","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046195","url":null,"abstract":"Ultra-deep sub-micron technologies are more vulnerable to different types of uncertainties. In this paper, we introduce a novel methodology to estimate the vulnerability of sequential circuits to soft errors at gate level. A new probabilistic modeling of SET propagation is proposed, which reduces the complexity of unrolling sequential circuits. This approach enables a multi-cycle error propagation analysis of sequential circuits using only two copies of the circuit combinational part. The proposed probabilistic modeling is based on the proposed backward unrolling approach in conjunction with the proposed formulation of SET propagation into a Satisfability problem by utilizing satisfability modulo theories. Useful information about the SET latency in sequential circuits and the minimum unrolling required to observe the actual behavior of the circuit is generated. These results are then used to estimate the circuit soft error rate. Experimental results demonstrate the effectiveness and applicability of the proposed approach.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126444242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
6T CMOS SRAMs reliability monitoring through stability measurements 通过稳定性测量监测6T CMOS sram的可靠性
B. Alorda, G. Torrens, S. Bota
{"title":"6T CMOS SRAMs reliability monitoring through stability measurements","authors":"B. Alorda, G. Torrens, S. Bota","doi":"10.1109/IOLTS.2017.8046239","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046239","url":null,"abstract":"Technology scaling trends led to an aggressive increase of SRAM cell sensitivity to process variation. More accurate and non-invasive methodologies must be considered to provide detailed bit-cell characterization focusing on writability margin. This work proposes a new metric using regular read/write operations based on the estimation of the maximum word-line voltage drop during write operations. The new writability metric reduces the hardware modification requirements achieving a correlation ratio near 0.94 with existing writability metrics. A customized memory circuit has been implemented in 65nm CMOS technology to demonstrate the capabilities of the new metric showing its dependence with the transistor width variation.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128488932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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