2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献_第5页

Diagnosis with transition faults on embedded segments 嵌入段过渡故障诊断

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046173

Theodoros Toulas, S. Tragoudas

引用次数: 0

BPPT — Bulk potential protection technique for hardened sequentials 强化序列的大容量电位保护技术

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046194

I. Nofal, A. Evans, A. He, G. Guo, Yuanqing Li, Li Chen, R. Liu, Haibin Wang, Mo Chen, S. Baeg, Shi-Jie Wen, R. Wong

引用次数: 0

Simulation-based analysis of FF behavior in presence of power supply noise 电源噪声下FF性能的仿真分析

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046211

Y. Miura, Takuya Yamamoto

引用次数: 1

SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs SICTA:一种基于sram的fpga的电路内叠加容错架构

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046168

Alexandra Kourfali, Amit Kulkarni, D. Stroobandt

引用次数: 3

Design of efficient error resilience in signal processing and control systems: From algorithms to circuits 信号处理和控制系统中有效的错误恢复设计:从算法到电路

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046241

J. Abraham, Suvadeep Banerjee, A. Chatterjee

{"title":"Design of efficient error resilience in signal processing and control systems: From algorithms to circuits","authors":"J. Abraham, Suvadeep Banerjee, A. Chatterjee","doi":"10.1109/IOLTS.2017.8046241","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046241","url":null,"abstract":"The proliferation of cyber physical systems in society, from the smart grid to sensor networks and robots has raised the importance of error resilience in signal processing and control systems to unprecedented levels. Resilience to errors in sensing and control algorithm execution in processors all the way down to circuits for sensing and actuation is of critical importance in safety-critical applications where undetected errors can have disastrous consequences. In this presentation, we describe how ideas in the domain of algorithm-based fault tolerance developed in the mid-80s for signal processing and matrix computations can be applied to a vast domain of circuits and systems in electrical engineering; from digital and analog filters to complex nonlinear autonomous control systems. The key insight is that electrical systems can be fundamentally represented by linear and nonlinear differential equations with equivalent matrix representations. These representations can be encoded with extra check states that bear a known relationship with all the observable states of the system independent of the system driving inputs. By checking for the validity of this relationship, errors can be detected and mitigated in real-time with near-zero latency with minimal hardware overhead. The broad vision of the proposed methodology is illustrated with examples from different electrical engineering domains.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124735778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Variation tolerant BTI monitoring in SRAM cells SRAM细胞耐变异BTI监测

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046203

Yiorgos Sfikas, Y. Tsiatouhas

引用次数: 9

On-line testing of sensor networks: A case study 传感器网络在线测试:一个案例研究

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046218

J. A. Miranda, A. Vaskova, M. Portela-García, M. García-Valderas, C. López-Ongil

引用次数: 0

Temporal redundancy latch-based architecture for soft error mitigation 基于时间冗余锁存的软错误缓解体系结构

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046245

Robert Schmidt, A. Ortiz, G. Fey

引用次数: 7

PUFMon: Security monitoring of FPGAs using physically unclonable functions PUFMon:使用物理不可克隆功能的fpga安全监控

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046216

Shahin Tajik, Julian Fietkau, Heiko Lohrke, Jean-Pierre Seifert, C. Boit

{"title":"PUFMon: Security monitoring of FPGAs using physically unclonable functions","authors":"Shahin Tajik, Julian Fietkau, Heiko Lohrke, Jean-Pierre Seifert, C. Boit","doi":"10.1109/IOLTS.2017.8046216","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046216","url":null,"abstract":"Mainstream FPGAs and programmable SoCs employ different countermeasures during configuration and runtime to mitigate physical attacks. However, it has been demonstrated that sophisticated active attack techniques, such as laser voltage probing, can still bypass the bitstream protections during the configuration phase. On the other hand, although the security monitoring IP cores provided by FPGA vendors can ensure the physical security during the runtime of applications, they are unable to detect such attacks during configuration. In this work, we propose a novel approach to using PUFs as physical sensors to monitor the integrity of FPGAs against active attacks. Small modifications in existing PUF architectures enable us to design a PUF-based security scheme, which can be deployed for integrity monitoring and authentication/key generation at the same time. We evaluate the effectiveness of our framework against a range of powerful attacks, such as optical probing and fault attacks. We further discuss how this scheme can be deployed during bitstream configuration in FPGAs with partial reconfiguration capability.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130403124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Design-time reliability evaluation for digital circuits 数字电路设计时可靠性评估

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046196

Mohamed A. Abufalgha, A. Bystrov

{"title":"Design-time reliability evaluation for digital circuits","authors":"Mohamed A. Abufalgha, A. Bystrov","doi":"10.1109/IOLTS.2017.8046196","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046196","url":null,"abstract":"A new method of evaluating the reliability of combinational circuits is proposed, this method uses two levels of characterisation: a Stochastic Fault Model (SFM) of the component library and a design-specific Critical Vector Model (CVM). The idea is to move the high-complexity problem of stochastic characterisation of parameters into the generic part of the design process, and do it just once for a great number of the specific designs. The SFM captures variations of the vector of parameters of a library component fault model, those causing a transient fault at the component output; it is meant to be supplied by the foundry, similar to timing library files. The CVM is derived by a limited number of simulation runs on the specific design, and represents the boundary between the erroneous and error-free operation, w.r.t. the vector of parameters of each component. The probability of error-free operation is subsequently calculated by jointly using SFM and CVM. The method is demonstrated on a chain of inverters for simplicity, and subsequently applied to a 3-bit full adder. A complex three-way trade-off between energy, performance and reliability is explored. The method is meant to serve as a basis for design-time reliability evaluation and runtime power-reliability management. A slow stage is added to the circuit under test to improve its reliability.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114787985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2