SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs

Abstract

Reassuring fault tolerance in computing systems that contain FPGA devices is the most important problem for mission critical space components. With the rise in interest of commercial SRAM-based FPGAs, it is crucial to provide runtime reconfigurable recovery from a failure. In this paper, we propose a superimposed virtual coarse-grained reconfigurable architecture, embedded with on-demand three level fault-mitigation technique. The proposed method performs run-time recovery via discrete microscrubbing. This approach can provide up to 3× faster runtime recovery with 10.2× less resources in FPGA devices, by providing integrated layers of fault mitigation.