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2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献

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Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms 通过访问模式调度放松DRAM刷新率:基于模板算法的案例研究
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-09-21 DOI: 10.1109/IOLTS.2017.8046197
Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, G. Karakonstantis
{"title":"Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms","authors":"Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, G. Karakonstantis","doi":"10.1109/IOLTS.2017.8046197","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046197","url":null,"abstract":"The main memory in today's systems is based on DRAMs, which may offer low cost and high density storage for large amounts of data but it comes with a main drawback; DRAM cells need to be refreshed frequently for retaining the stored data. The refresh rate in modern DRAMs is set based on the worst-case retention time without considering access statistics, thereby resulting in very frequent refresh operations. Such high refresh rate leads eventually to large power and performance overheads, which are increasing with higher DRAM densities. However, such high refresh rates may not even required due to extremely low probability of the actual occurrence of the assumed worst-case scenarios, or due to the implicit refresh operation that occur during every memory access, a feature that has not been yet been studied in depth. In this paper, we enhance the state-of-the-art by systematically exploiting the implicit refresh of memory access for relaxing the refresh rate, while minimizing the resulting memory errors. This is achieved by modifying the algorithmic parameters that influence the access patterns such that all stored data are being touched within a target time interval that is necessary for meeting a target error rate. The proposed method is applied to stencil-based algorithms which represent a wide class of algorithms used in numerical analysis, image processing and cellular automata applications. The efficacy of the proposed method is demonstrated on an off-the-shelf server running a fully fledged Linux OS and results show that it is even possible to completely disable DRAM refresh with minor quality loss.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121279212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Hardware Trojan detection and classification based on steady state learning 基于稳态学习的硬件木马检测与分类
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-09-19 DOI: 10.1109/IOLTS.2017.8046225
Masaru Oya, M. Yanagisawa, N. Togawa
{"title":"Hardware Trojan detection and classification based on steady state learning","authors":"Masaru Oya, M. Yanagisawa, N. Togawa","doi":"10.1109/IOLTS.2017.8046225","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046225","url":null,"abstract":"In this paper, we propose a logic-testing based HT detection and classification method utilizing steady state learning. We first observe that HTs are hidden while applying random test patterns in a short time but most of them can be activated in a very long-term random circuit operation. Hence it is very natural that we learn steady signal-transition states of every suspicious Trojan net in a netlist by performing short-term random simulation. After that, we simulate or emulate the netlist in a very long time by giving random test patterns and obtain a set of signal-transition states. By discovering correlation between them, our method detects HTs and finds out its behavior. Experimental results demonstrate that our method can successfully identify all the real Trojan nets to be Trojan nets and all the normal nets to be normal nets, while other existing logic-testing HT detection methods cannot detect some of them.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121831940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new 3-bit burst-error correcting code 一种新的3位突发错误纠错码
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046167
A. Klockmann, G. Georgakos, M. Gössel
{"title":"A new 3-bit burst-error correcting code","authors":"A. Klockmann, G. Georgakos, M. Gössel","doi":"10.1109/IOLTS.2017.8046167","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046167","url":null,"abstract":"In this paper a new 3-bit burst-error correcting code is proposed. Compared to a 1-bit error correcting Hamming code only two additional check bits are needed and compared to a 3-bit burst-error correcting Burton code the number of check bits can be reduced by 2. Since the proposed code is systematically designed by use of finite field algebra the code can be determined for an arbitrary word length and decoding is simple. Examples for different word length with up to about 1000 bits are described. The proposed code can correct single bit errors, adjacent two-bit errors, adjacent 3-bit errors and nearly adjacent 2-bit errors and may be useful for error correction in registers or register arrays, in combinational circuits and also in memories for which data-multiplexing is not used.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132353210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Test pattern generation to detect multiple faults in ROBDD based combinational circuits 基于ROBDD的组合电路中多故障检测的测试模式生成
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046223
Toral Shah, A. Matrosova, Virendra Singh
{"title":"Test pattern generation to detect multiple faults in ROBDD based combinational circuits","authors":"Toral Shah, A. Matrosova, Virendra Singh","doi":"10.1109/IOLTS.2017.8046223","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046223","url":null,"abstract":"Deduced Ordered Binary Decision Diagram (ROBDD) based circuit syntheses is known to have complete testability under single stuck-at, multiple stuck-at and path delay fault models. In this paper we propose a test generation methodolgy for ROBDD based implementations. The test vectors required for all multiple stuck-at faults and delay faults are derived from the disjoint sum-of-products(DSOPs) representation thereby allowing test generation at design time with minimum effort.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130600439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SIFI: AMD southern islands GPU microarchitectural level fault injector SIFI: AMD南岛GPU微架构级故障注入器
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046209
Alessandro Vallero, D. Gizopoulos, S. Carlo
{"title":"SIFI: AMD southern islands GPU microarchitectural level fault injector","authors":"Alessandro Vallero, D. Gizopoulos, S. Carlo","doi":"10.1109/IOLTS.2017.8046209","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046209","url":null,"abstract":"General Purpose computing on Graphics Processing Unit offers a remarkable speedup for data parallel workloads, leveraging GPUs computational power. However, differently from graphic computing, it requires highly reliable operation in several application domains. In this paper we present SIFI a reliability evaluation framework for soft-errors on AMD GPUs built on top of Multi2Sim, a micro-architectural level simulator. SIFI is capable of computing different reliability metrics by means of two different techniques: fault injection and ACE analysis. Experiments performed on a set of 14 GPGPU applications targeting the AMD Southern Islands GPU architecture show the capability of the tool and the potential of its use to support decisions about the best architectural parameters for a given application.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133244340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance VPUF:基于投票人的物理不可克隆函数，具有高可靠性和建模抗攻击能力
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046200
Jing Ye, Yu Hu, Xiaowei Li
{"title":"VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance","authors":"Jing Ye, Yu Hu, Xiaowei Li","doi":"10.1109/IOLTS.2017.8046200","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046200","url":null,"abstract":"Physical Unclonable Function (PUF) has broad application prospects in the field of hardware security. Arbiter PUF is a typical PUF, but is threatened by modeling attacks. To resist attack, XOR arbiter PUF employs multiple basic arbiter PUFs and XOR their response bits to generate the final response bit. However, its low reliability not only limits its applications, but also leaks information to enhance modeling attacks. To improve both the reliability and the modeling attack resistance, we propose the Voter based PUF (VPUF), which also employs multiple basic arbiter PUFs. It has two key components: (1) an on-line reliability checker to evaluate the reliability level of each internal response bit produced by each basic arbiter PUF; (2) a weighted voter, instead of XOR gates, to produce the final response bit. Experiments in FPGAs show 7.6%∼23.4% reliability improvement of the VPUF than the XOR arbiter PUF, and prove the VPUF can resist modeling attacks.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123443972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Reliability of computing systems: From flip flops to variables 计算系统的可靠性:从触发器到变量
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046242
G. D. Natale, Maha Kooli, A. Bosio, M. Portolan, R. Leveugle
{"title":"Reliability of computing systems: From flip flops to variables","authors":"G. D. Natale, Maha Kooli, A. Bosio, M. Portolan, R. Leveugle","doi":"10.1109/IOLTS.2017.8046242","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046242","url":null,"abstract":"Reliability evaluation is a critical task in computing systems. From one side, the results must be accurate enough not to under-or over-estimate the overall system reliability (thus either resulting in a non-reliable system, or a system for which too expensive solutions have been adopted). On the other side, the time required for the analysis should be kept at the minimum. This paper presents some new advances in the reliability assessment of computing systems, by showing techniques targeting both hardware and software levels, and the combination of both.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117002685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware Trojans classification for gate-level netlists using multi-layer neural networks 基于多层神经网络的门级网络硬件木马分类
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046227
Kento Hasegawa, M. Yanagisawa, N. Togawa
{"title":"Hardware Trojans classification for gate-level netlists using multi-layer neural networks","authors":"Kento Hasegawa, M. Yanagisawa, N. Togawa","doi":"10.1109/IOLTS.2017.8046227","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046227","url":null,"abstract":"Recently, due to the increase of outsourcing in IC design and manufacturing, it has been reported that malicious third-party IC vendors often insert hardware Trojans into their products. Especially in IC design step, it is strongly required to detect hardware Trojans because malicious third-party vendors can easily insert hardware Trojans in their products. In this paper, we propose a machine-learning-based hardware-Trojan detection method for gate-level netlists using multi-layer neural networks. First, we extract 11 Trojan-net feature values for each net in a netlist. After that, we classify the nets in an unknown netlist into a set of Trojan nets and that of normal nets using multi-layer neural networks. We obtained at most 100% true positive rate with our proposed method.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116935110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 68
Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack 多态PUF:利用CPU+FPGA SoC的可重构性来抵御建模攻击
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046220
Jing Ye, Yue Gong, Yu Hu, Xiaowei Li
{"title":"Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack","authors":"Jing Ye, Yue Gong, Yu Hu, Xiaowei Li","doi":"10.1109/IOLTS.2017.8046220","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046220","url":null,"abstract":"Physical Unclonable Function {PUF) is severely threatened by modeling attacks. This paper proposes a novel Polymorphic PUF for CPU+FPGA SoC. We fully exploit the dynamic reconfigurability of the SoC to minimize the Challenge Response Pair (CRP) correlation so as to resist modeling attacks. An asymmetric RO pair is proposed to produce the response. Experiments on real CPU+FPGA SoCs show the high resistance of Polymorphic PUF against modeling attacks, with good uniformity and uniqueness.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134579854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687 基于IEEE 1687的自感知片上系统可靠性管理框架
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046166
Ahmed M. Y. Ibrahim, H. Kerkhoff
{"title":"A cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687","authors":"Ahmed M. Y. Ibrahim, H. Kerkhoff","doi":"10.1109/IOLTS.2017.8046166","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046166","url":null,"abstract":"A cost-efficient framework for executing life-time dependability procedures is presented in this paper. The proposed framework relies on distributed sensors and actuators (embedded instruments) for self-awareness and adaptation, where the IEEE 1687 standard (iJTAG) is utilized for the dependability communications and the on-chip access of the instruments.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132771644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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