2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献_第2页

Probabilistic error detection and correction in switched capacitor circuits using checksum codes 使用校验和码的开关电容电路的概率错误检测和校正

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046233

Md Imran Momtaz, Suvadeep Banerjee, A. Chatterjee

{"title":"Probabilistic error detection and correction in switched capacitor circuits using checksum codes","authors":"Md Imran Momtaz, Suvadeep Banerjee, A. Chatterjee","doi":"10.1109/IOLTS.2017.8046233","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046233","url":null,"abstract":"In the past, techniques for error detection in linear digital and analog circuits using checksum codes have been developed and shown to be highly efficient. While error detection is a solved problem, error correction has proved to be difficult due to the time and area overheads involved in diagnosing failed system states and correcting them in real-time. To solve the correction problem, real-time probabilistic correction mechanisms have been proposed for digital circuits that correct for state errors in a probabilistic manner, circumventing the process of accurate error diagnosis. Such a technique is difficult to apply to continuous-time analog circuits without altering the analog transfer function, due to the nature of error feedback mechanisms involved. However, switched-capacitor circuits offer intrinsic advantages; they replicate analog continuous-time behavior while retaining the benefits of a digital clock. In this work, we show how errors in switched-capacitor circuits can be detected and corrected, using probabilistic correction algorithms, by taking advantage of the separation in time afforded by the use of a digital clock between error-free and error-affected clock cycles of the circuit. By probabilistically correcting errors in real-time before the onset of future clock cycles, the advantages offered by digital clocks are exploited to deliver high-fidelity analog performance in switched-capacitor filters resulting in significant SNR benefits at low cost.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130460556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Voltage margins identification on commercial x86-64 multicore microprocessors 商用x86-64多核微处理器的电压裕度识别

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046198

G. Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Charalampos Magdalinos, D. Gizopoulos

{"title":"Voltage margins identification on commercial x86-64 multicore microprocessors","authors":"G. Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Charalampos Magdalinos, D. Gizopoulos","doi":"10.1109/IOLTS.2017.8046198","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046198","url":null,"abstract":"In this paper, we explore the pessimistic voltage guardbands of two multicore x86-64 microprocessor chips that belong to different microarchitectures (one ultra-low power and one high-performance microprocessor), when programs are executed on individual cores of the CPU chips. We also examine the energy and temperature gains as positive effects of lowering the voltage in both chips while preserving the functional correctness of programs. The behavior of the cores was examined executing 8 different workloads from the SPEC CPU2006 suite. Our differential experimental study is performed on two state-of-the-art x86-64 microprocessors: an ultra-low power Intel Core i5-4200U and a high-performance Intel Core i7-3970X. Based on the results, the cores on each microprocessor chip behave differently for different workloads when undervolted, and the voltage guardbands are more than 15% below the nominal voltage levels. We show that the energy efficiency can be increased by a maximum of 20% and the reduction of temperature can be up to 25%.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116355149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Robustness in automotive electronics: An industrial overview of major concerns 汽车电子的稳健性:主要关注的工业概述

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-03 DOI: 10.1109/IOLTS.2017.8046234

Ulrich Backhausen, O. Ballan, P. Bernardi, S. D. Luca, Julie Henzler, T. Kern, D. Piumatti, Thomas Rabenalt, Krishnapriya Chakiat Ramamoorthy, E. Sánchez, A. Sansonetti, R. Ullmann, F. Venini, R. Wiesner

引用次数: 8

Investigation of critical path selection for in-situ monitors insertion 原位监测仪插入关键路径选择研究

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046229

F. Cacho, A. Benhassain, R. Shah, S. Mhira, V. Huard, L. Anghel

引用次数: 4

On-line monitoring of system health using on-chip SRAMs as a wearout sensor 利用片上sram作为磨损传感器对系统健康状况进行在线监测

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046230

Woongrae Kim, Taizhi Liu, L. Milor

引用次数: 2

Jamming resistant encoding for non-uniformly distributed information 非均匀分布信息的抗干扰编码

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046213

Batya Karp, Yerucham Berkowitz, O. Keren

引用次数: 3

Weighted logic locking: A new approach for IC piracy protection 加权逻辑锁:一种保护IC盗版的新方法

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046226

Nikos Karousos, Konstantinos Pexaras, Irene G. Karybali, E. Kalligeros

{"title":"Weighted logic locking: A new approach for IC piracy protection","authors":"Nikos Karousos, Konstantinos Pexaras, Irene G. Karybali, E. Kalligeros","doi":"10.1109/IOLTS.2017.8046226","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046226","url":null,"abstract":"Logic locking has been successfully used for protecting digital circuits against IC piracy. Modern logic locking techniques offer significant security advantages, like high corruptibility of the locked circuit's outputs when applying random keys (= 50% Hamming Distance-HD-compared to the correct outputs), or resilience to the key-sensitization attack. However, there are no techniques to combine both advantages. To solve this problem, weighted logic locking is proposed in this paper. Instead of the conventional single key-input control, the proposed technique uses multiple key-inputs to control every key-gate. This new, weighted key-gate control is by construction immune to the key-sensitization attack, while by employing a new key-gate insertion metric, 50% HD is obtained even for circuits with many outputs. Additionally, weighted key-gate control increases dramatically the probability of any key-gate to corrupt the circuit's values, which means that fewer key-gates are needed to achieve 50% HD. This way, execution time for locking the circuits is drastically reduced. Apart from these advantages, weighted logic locking is fairly “generic” and can be combined with other techniques to improve security (e.g., to thwart the SAT attack).","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129645720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A generic embedded sequence generator for constrained-random validation with weighted distributions 基于加权分布的约束随机验证通用嵌入式序列生成器

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046199

Xiaobing Shi, N. Nicolici

引用次数: 0

Cache timing attacks countermeasures and error detection in Euclidean addition chains based scalar multiplication algorithm for elliptic curves 基于欧氏加法链的椭圆曲线标量乘法算法的缓存定时攻击对策和错误检测

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046212

Fangan-Yssouf Dosso, P. Véron

引用次数: 1

Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs 基于sram的fpga TMR结构中辐射诱导的跨域误差分析

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046214

L. Sterpone, L. Boragno

{"title":"Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs","authors":"L. Sterpone, L. Boragno","doi":"10.1109/IOLTS.2017.8046214","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046214","url":null,"abstract":"SRAM-Based FPGAs represent a low-cost alternative to ASIC device thanks to their high performance and design flexibility. In particular, for aerospace and avionics application fields, SRAM-based FPGAs are increasingly adopted for their configurability features making them a viable solution for long-time applications. However, these fields are characterized by a radiation environment that makes the technology extremely sensitive to radiation-induced Single Event Upsets (SEUs) in the SRAM-based FPGA's configuration memory. Configuration scrubbing and Triple Modular Redundancy (TMR) have been widely adopted in order to cope with SEU effects. However, modern FPGA devices are characterized by a heterogeneous routing resource distribution and a complex configuration memory mapping causing an increasing sensitivity to Cross Domain Errors affecting the TMR structure. In this paper we developed a new methodology to calculate the reliability of TMR architecture considering the intrinsic characteristics of the new generation of SRAM-based FPGAs. The method includes the analysis of the configuration bit sharing phenomena and of the routing long lines. We experimentally evaluate the method of various benchmark circuits evaluating the Mean Upset To Failure (MUTF). Finally, we used the results of the developed method to implement an improved design achieving 29x improvement of the MUTF.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121663577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8