2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献_第4页

Dynamic aging compensation and Safety measures in Automotive environment 汽车环境下动态老化补偿及安全措施

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046204

S. Mhira, V. Huard, A. Benhassain, F. Cacho, S. Naudet, A. Jain, C. Parthasarathy, A. Bravaix

引用次数: 0

Instruction-based self-test for delay faults maximizing operating temperature 基于指令的延迟故障自检，最大限度地提高工作温度

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046231

N. Hage, Rohini Gulve, M. Fujita, Virendra Singh

{"title":"Instruction-based self-test for delay faults maximizing operating temperature","authors":"N. Hage, Rohini Gulve, M. Fujita, Virendra Singh","doi":"10.1109/IOLTS.2017.8046231","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046231","url":null,"abstract":"In today's technology, reliability is one of the major challenges. Process variations and increasing power density in advanced technology nodes make the condition even worse. Process variations during manufacturing induce delay variations and such variations may manifest into faults at the higher temperature during operation. Delay faults at higher functional temperature is a critical factor for the reliability of a system. Current DFT-based methods do not handle this properly. In this paper, we propose an instruction based self-test (IBST) technique to elevate the temperature of a chip near to functional temperature and test it for delay faults at that temperature. In the first step, integer linear programming (ILP) is used to find out power hungry instructions. These instructions cause maximum toggling in a unit. In the second step, delay test instructions are combined to create a program for testing functional unit of an out-of-order superscalar processor. Experimentation of the proposed technique is carried out on portable ISA (PISA) based superscalar processor. Higher operating temperature 95°C ± 2°C is achieved and it is maintained while applying delay test.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133226122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An on-line test strategy and analysis for a 1T1R crossbar memory 1T1R交叉棒存储器在线测试策略与分析

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046206

Manuel Escudero-Lopez, F. Moll, A. Rubio, I. Vourkas

引用次数: 4

Fast power overhead prediction for hardware redundancy-based fault tolerance 基于硬件冗余容错的快速电力开销预测

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046232

S. Scharoba, H. Vierhaus

引用次数: 1

Minimal exercise vector generation for reliability improvement 最小的运动矢量生成的可靠性改进

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046205

P. M. Reddy, Stavros Hadjitheophanous, V. Soteriou, Paul V. Gratz, M. Michael

{"title":"Minimal exercise vector generation for reliability improvement","authors":"P. M. Reddy, Stavros Hadjitheophanous, V. Soteriou, Paul V. Gratz, M. Michael","doi":"10.1109/IOLTS.2017.8046205","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046205","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) is a prominent physical failure mechanism which severely degrades the performance of PMOS transistors whenever the voltage at the gate is negatively biased. It leads to catastrophic timing violations in critical circuits and a severe shortening of the overall operational lifetime of the entire system. To alleviate such damaging effects due to NBTI, we present PRITEXT, a novel technique which generates a minimal set of deterministic exercise vectors based on test generation techniques which inherently near-optimizes the bit patterns across each of the generated vectors; the end target being to exercise the critical paths of a device when dormant so as to achieve near-ideal NBTI stress reduction. We explore the design-space of our generated vectors and apply them to our test processor platform under differing sequences, where our evaluation under realistic benchmarks shows that PRITEXT leads to an average 4.99× and a maximum of 13.91× lifetime improvement using 9 generated vectors. In an attempt to reduce hardware overheads even further, we next propose a heuristic to further reduce the number of exercise vectors with minimum loss in lifetime improvement.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114902781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Automating wafer-level test of uncooled infrared detectors using wafer-prober 利用晶圆探测器对非冷却红外探测器进行晶圆级自动测试

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046170

M. Makhlouf, D. Goller, Lutz Gendrisch, S. Kolnsberg, F. Vogt, A. Utz, D. Weiler, H. Vogt

{"title":"Automating wafer-level test of uncooled infrared detectors using wafer-prober","authors":"M. Makhlouf, D. Goller, Lutz Gendrisch, S. Kolnsberg, F. Vogt, A. Utz, D. Weiler, H. Vogt","doi":"10.1109/IOLTS.2017.8046170","DOIUrl":"https://doi.org/10.1109/IOLTS.2017.8046170","url":null,"abstract":"Fraunhofer IMS develops and fabricates far-infrared focal plane arrays (IRFPA) using microbolometers with a pixel pitch of 17μm technology realized on top of a 0.35 μm CMOS readout integrated circuit (ROIC). The microbolometers are encapsulated by a Chip-Scale-Package (CSP) to ensure a high quality vacuum level. The CSP is realized by placing an infrared transparent lid above a solder frame surrounding the microbolometer array. To concept a wafer-level test it is very challenging to implement highly accurate electrical stimuli and a far infrared radiation source (black body) while affecting the wafer-prober handling by a non-flat wafer surface, due to the infrared transparent lids of the CSP. Accordingly, wafer-level test has been developed based on a PC which controls, by using a test program, the wafer handling of a prober, the electrical stimuli of a test hardware, and the far-infrared radiation such as the optical stimuli. Thus, the most important electro-optical parameters of IRFPAs will be measured at wafer-level: Noise Equivalent Temperature Difference (NETD), responsivity, and the percentage of the defective pixels.","PeriodicalId":233462,"journal":{"name":"2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"323 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122098404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Thermal laser attack and high temperature heating on HfO2-based OxRAM cells 基于hfo2的OxRAM电池的热激光攻击和高温加热

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046202

A. Krakovinsky, M. Bocquet, R. Wacquez, J. Coignus, J. Portal

引用次数: 6

Reliable gas sensing with memristive array 可靠的气体传感忆阻阵列

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046228

Adedotun Adeyemo, A. Jabir, J. Mathew, E. Martinelli, C. Natale, M. Ottavi

引用次数: 4

Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution 基于mtj的内存逻辑全加法器的软错误分析:威胁与解决方案

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046221

Javad Talafy, H. Zarandi

引用次数: 5

On the in-field test of embedded memories 关于嵌入式记忆的现场测试

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2017-07-01 DOI: 10.1109/IOLTS.2017.8046236

P. Bernardi, Marco Restifo, E. Sánchez, M. Reorda

引用次数: 3