6T CMOS SRAMs reliability monitoring through stability measurements

Abstract

Technology scaling trends led to an aggressive increase of SRAM cell sensitivity to process variation. More accurate and non-invasive methodologies must be considered to provide detailed bit-cell characterization focusing on writability margin. This work proposes a new metric using regular read/write operations based on the estimation of the maximum word-line voltage drop during write operations. The new writability metric reduces the hardware modification requirements achieving a correlation ratio near 0.94 with existing writability metrics. A customized memory circuit has been implemented in 65nm CMOS technology to demonstrate the capabilities of the new metric showing its dependence with the transistor width variation.