2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第2页

1.2 nW Neuromorphic Enhanced Wake-Up Radio 1.2 nW神经形态增强唤醒无线电

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893247

Zalfa Jouni, Thomas Soupizet, Siqi Wang, A. Benlarbi-Delai, Pietro M. Ferreira

引用次数: 2

A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications 面向区块链物联网应用的灵活节能BLAKE-256/2s协处理器

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893257

Pham Hoai Luan, T. Tran, V. Le, Y. Nakashima

{"title":"A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications","authors":"Pham Hoai Luan, T. Tran, V. Le, Y. Nakashima","doi":"10.1109/SBCCI55532.2022.9893257","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893257","url":null,"abstract":"Developing flexible and energy-efficient BLAKE-256/2s hardware has recently become necessary since BLAKE-256 and BLAKE2s are important cryptographic hash functions in reliability and security enhancement for blockchain-based IoT applications. However, previous BLAKE-256/2s architectures are challenging in achieving high flexibility and energy efficiency. Therefore, this paper proposes the BLAKE-256/2s co-processor to achieve high flexibility and energy efficiency for blockchain-based IoT applications. The proposed BLAKE-256/2s accelerator has three novel optimization techniques to achieve those goals. First, a configurable hashing core is proposed to enhance flexibility. Second, a pipelined permutation and compression architecture are developed to improve the throughput and hardware efficiency. Third, a mining transmission mechanism is introduced to optimize the performance of our co-processor at the system-on-chip level. The proposed co-processor is implemented and verified on a Xilinx Zynq $mathbf{UltraScale}+$ MPSoC ZCU102 FPGA. Accordingly, the power and energy efficiency of the co-processor on the ZCU102 FPGA is significantly better than the Intel i9 10940X CPU and the RTX 3090 GPU. Moreover, experimental results on several FPGAs prove that the proposed co-processor is considerably higher throughput, area efficiency, and flexibility than FPGA-based related works.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122464749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Edge GPU based on an FPGA Overlay Architecture using PYNQ 基于FPGA覆盖架构的边缘GPU使用PYNQ

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893229

Hector Gerardo Muñoz Hernandez, Florian Fricke, Muhammed Al Kadi, M. Reichenbach, Michael Hübner

{"title":"Edge GPU based on an FPGA Overlay Architecture using PYNQ","authors":"Hector Gerardo Muñoz Hernandez, Florian Fricke, Muhammed Al Kadi, M. Reichenbach, Michael Hübner","doi":"10.1109/SBCCI55532.2022.9893229","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893229","url":null,"abstract":"Using Graphical Processing Units (GPUs) to accelerate applications such as Deep Neural Networks (DNNs) or image processing tasks has been gaining lots of attention for some time now due to their high performance. This has brought a lot of attention to creating toolflows where hardware designing expertise is not a requirement anymore, resulting in making the technology accessible to as many users as possible. However, hardware knowledge is still important to make the toolflows run efficiently on the target platform. In this paper, we introduce a framework that uses Jupyter Notebooks, a browser based interactive computing environment, and PYNQ which is as a high-level-abstraction interface between the Programmable Logic (PL) and the Processing System (PS) from which the user can unlock the full potential of a highly customizable soft-core GPU running on an Field-programmable Gate Array (FPGA). The framework is open-source and requires only a few set-up steps to get applications running by re-using the existing Jupyter Notebooks as templates, making it ideal for fast prototyping and educational purposes. Moreover, there is also the possibility to customize the architecture of the target hardware to fit performance, resource utilization, and functional requirements. This framework also supports floating-point operations and can be ported to System on Chip (SoC) devices like the Xilinx Zynq-7000 family, among others.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122241971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Digital Defect-Oriented Test Methodology for Flipped Voltage Follower Low Dropout (LDO) Voltage Regulators 翻转电压从动器低差(LDO)稳压器数字缺陷导向测试方法

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893243

M. Saikiran, Mona Ganji, Degang Chen

{"title":"Digital Defect-Oriented Test Methodology for Flipped Voltage Follower Low Dropout (LDO) Voltage Regulators","authors":"M. Saikiran, Mona Ganji, Degang Chen","doi":"10.1109/SBCCI55532.2022.9893243","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893243","url":null,"abstract":"Low Dropout (LDO) voltage regulator is one of the most commonly used blocks in integrated circuits (IC). In contrast to classic LDOs, flipped voltage follower (FVF) LDOs are capable of sourcing high current loads as well as providing high bandwidth (increased PSRR) due to the presence of a fast local loop. In mission-critical applications such as automotive, industrial, and space applications, functional safety (FuSa) is a very important requirement. To emphasize this requirement, ISO26262 Standard for functional safety recommends an automotive IC to have a very high defect coverage (usually greater than 90%). In this work, we propose an extremely simple and low-cost defect detection methodology for a folded FVF LDO providing high defect-coverage. Furthermore, as the proposed method is time-efficient, it can also be incorporated wafer-level production testing of the SoC and reduce the test time. The proposed design for test (DfT) defect detection method uses completely digital injection and detection circuits, making the method robust and easy to implement. Additionally, the digital nature of the method makes it an ideal candidate in an SoC where digital control and monitor bus (like IJTAG) is already available. The circuit under test (CUT) used in this work is designed in 65nm UMC technology. In this paper, in addition to the defect coverage results with the proposed method, we also present defect-coverage results for our CUT with defect detection methods proposed in the literature for comparison. The transistor-level fault simulations confirm that the proposed method has high fault coverage of 94% with less than 4% area overhead making it extremely area-efficient.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126999712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Virtual Board Approach for Prototyping and Teaching Digital Design 虚拟板的原型设计与数字设计教学

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893259

Alcides S. Costa, Leonardo Droves Silveira, A. Reis

引用次数: 1

A distributed Embedded Systems IoT platform and Associated services Supporting Shopping Cart for Disabled People 一种支持残疾人购物车的分布式嵌入式系统物联网平台及相关服务

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893262

K. Antonopoulos, D. Karadimas, Alexandros Spournias, C. Panagiotou, Ignantios Fwtiou, Ioannis Symeonidis, Christos D. Antonopoulos, Michael Hübner, N. Voros

{"title":"A distributed Embedded Systems IoT platform and Associated services Supporting Shopping Cart for Disabled People","authors":"K. Antonopoulos, D. Karadimas, Alexandros Spournias, C. Panagiotou, Ignantios Fwtiou, Ioannis Symeonidis, Christos D. Antonopoulos, Michael Hübner, N. Voros","doi":"10.1109/SBCCI55532.2022.9893262","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893262","url":null,"abstract":"Over the last few years advancements in technological domains such as embedded system, IoT and distributed communication have greatly propelled the development of platforms and systems enabling people with disabilities to equally participate in everyday life activities. The added value of such platforms is even more pronounced when respective activities are of outmost importance like going to the supermarket and performing all the functions and services that a person without impairments can enjoy. In this context this paper presents and analyzes an end-to-end architecture where, distributed embedded systems intelligence, distributed data communication techniques and open data interfaces approaches are leveraged so that people with mobility impairments can be fully independent and functional when visiting a supermarket. In-depth analysis is offered on critical components and services such as, the specialized cart movement control unit, multifaceted localization techniques and automated pricing and merchandize management services. It is noted that this work is the outcome of a Greek National Research project supported by one of the biggest supermarket companies in Greece.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134200723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An All-digital Programmable Current-limited Discharge Circuitry for a Safe Electrical Stimulation 用于安全电刺激的全数字可编程限流放电电路

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893246

Reza Ranjandish

引用次数: 0

Miniaturized Sign-Magnitude Stochastic-Binary FIR Filter Architecture with Enhanced Accuracy 具有增强精度的小型化符号-幅度随机二值FIR滤波器结构

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893252

Gayas Sayed, M. Kuhl

{"title":"Miniaturized Sign-Magnitude Stochastic-Binary FIR Filter Architecture with Enhanced Accuracy","authors":"Gayas Sayed, M. Kuhl","doi":"10.1109/SBCCI55532.2022.9893252","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893252","url":null,"abstract":"This paper presents a stochastic-binary hybrid ar-chitecture for miniaturizing FIR filters and its comparison with established filter implementations. FPGA realization of 4-, 16-and 64-tap FIR filters with 8-bit word length has confirmed the worthiness of the proposed architecture in densely packed systems. FPGA resources reduces by $sim 53%$ in a 4 - tap FIR filter, with the architecture's area efficiency increasing with filter taps. This hybrid architecture, performing multiplication in stochastic and accumulation in binary domain, requires only 2 random number generators, one for tapped delay-line and the other for filter coefficients. Thanks to additive-recurrence-based low-discrepancy sequences in stochastic number generators and non-scaled binary accumulation, the proposed stochastic architecture achieves best-in-class performance. This is validated via a detailed analysis of a 16-tap filter that achieves a pass-band ripple of $A_{p}=0.58dB$ and a stop-band attenuation of $A_{st}=-31.46dB$, making it indistinguishable from binary implementations. Additionally, a mathematical approach is pre-sented to estimate the error in the filter output, well before its actual realization. ASIC synthesis of a 16-tap FIR filter based on the proposed architecture with area of only 30,165 $mu m^{2}$ is superior to all discussed filter structures: It grants 68% area reduction compared to its binary counterpart and consumes an energy per operation of 0.429 nJ, a value at least $1.8times$ lower than previous stochastic designs.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122938718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A custom interconnection multi-FPGA framework for distributed processing applications 分布式处理应用的自定义互连多fpga框架

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893238

C. Salazar-García, A. Chacón-Rodríguez, R. Rímolo-Donadío, R. García-Ramírez, David Solórzano-Pacheco, Jeferson González-Gómez, C. Strydis

{"title":"A custom interconnection multi-FPGA framework for distributed processing applications","authors":"C. Salazar-García, A. Chacón-Rodríguez, R. Rímolo-Donadío, R. García-Ramírez, David Solórzano-Pacheco, Jeferson González-Gómez, C. Strydis","doi":"10.1109/SBCCI55532.2022.9893238","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893238","url":null,"abstract":"The development of multi-FPGA systems focused on high-performance computing requires high-speed channels, low bandwidth overhead and latency. In this paper, we propose a multi-FPGA interconnection framework aimed at distributed processing applications. Our solution allows efficient communication between different processing elements distributed among the FPGAs. To evaluate our proposal, we built a multi-FPGA system composed of five Zynq ZC706 FPGA boards capable of hosting a diverse number of coprocessors distributed over our custom network. With an aggregate bandwidth of up to 25 Gbps per FPGA board, the interconnection framework reaches a latency of only 200.36 ns, one of the lowest reported in the lElectronics Engineering, iterature. Experimental results show a computational efficiency of 97.25 % with a sustained throughput of 21.4 GFLOPS. Furthermore, the proposed network interconnection architecture is easily portable to the latest generation FPGAs. This makes the current proposal a competitive option for distributed processing in multi-FPGA systems.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127072842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Limits for Low Supply Voltage Operation of a 5 GHz VCO to Drive a 4-Path Mixer 5 GHz压控振荡器驱动4路混频器的低电源电压操作限制

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893254

Mariana Siniscalchi, C. Galup-Montoro, S. Bourdel, F. Silveira

引用次数: 0