Digital Defect-Oriented Test Methodology for Flipped Voltage Follower Low Dropout (LDO) Voltage Regulators

Abstract

Low Dropout (LDO) voltage regulator is one of the most commonly used blocks in integrated circuits (IC). In contrast to classic LDOs, flipped voltage follower (FVF) LDOs are capable of sourcing high current loads as well as providing high bandwidth (increased PSRR) due to the presence of a fast local loop. In mission-critical applications such as automotive, industrial, and space applications, functional safety (FuSa) is a very important requirement. To emphasize this requirement, ISO26262 Standard for functional safety recommends an automotive IC to have a very high defect coverage (usually greater than 90%). In this work, we propose an extremely simple and low-cost defect detection methodology for a folded FVF LDO providing high defect-coverage. Furthermore, as the proposed method is time-efficient, it can also be incorporated wafer-level production testing of the SoC and reduce the test time. The proposed design for test (DfT) defect detection method uses completely digital injection and detection circuits, making the method robust and easy to implement. Additionally, the digital nature of the method makes it an ideal candidate in an SoC where digital control and monitor bus (like IJTAG) is already available. The circuit under test (CUT) used in this work is designed in 65nm UMC technology. In this paper, in addition to the defect coverage results with the proposed method, we also present defect-coverage results for our CUT with defect detection methods proposed in the literature for comparison. The transistor-level fault simulations confirm that the proposed method has high fault coverage of 94% with less than 4% area overhead making it extremely area-efficient.