2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献

Secure Communication with Peripherals in NoC-based Many-cores 基于网络的多核外设安全通信

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893244

R. Faccenda, Gustavo Comarú, L. L. Caimi, F. Moraes

{"title":"Secure Communication with Peripherals in NoC-based Many-cores","authors":"R. Faccenda, Gustavo Comarú, L. L. Caimi, F. Moraes","doi":"10.1109/SBCCI55532.2022.9893244","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893244","url":null,"abstract":"Many-core systems-on-chip (MCSoCs) contain pro-cessing elements (PEs), peripherals attached to the system, and an NoC connecting them. These systems have different flows traversing the NoC: PE-PE and PE-peripheral flows. Malicious hardware or software can hinder system security due to the resource sharing feature, such as CPU sharing for multitasking or sharing NoC links for flows belonging to different applications. Methods that isolate applications with security constraints, such as Secure Zones (SZs), protect PE-PE flows against most of the attacks reported in the literature. Proposals with methods to secure the communication with peripherals in the literature are scarce, with most of them focusing on shared memory protection. This paper presents an original approach, Secure Mapping with Access Point - SeMAP, which creates mapping policies for SZs, and communication strategies with IO devices, to protect PE-peripheral flows. Results show that the application execution time is not penalized by applying SeMAP, presenting advantages compared to a state-of-the-art approach. In terms of security, SeMAP successfully resisted an attack campaign, blocking malicious packets attempting to enter the SZ.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123113837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

eSi-BTC: an energy efficient Bitcoin mining core eSi-BTC:高效节能的比特币挖矿核心

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893218

C. Gewehr, Carlis Raupp, J. Leao

引用次数: 0

Error Resilience Evaluation of Approximate Storage in the Intra Prediction of VVC Decoders 近似存储在VVC解码器帧内预测中的容错性评价

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893263

Matheus Isquierdo, Renira Soares, F. Sampaio, B. Zatt, D. Palomino

引用次数: 2

Methodology for an Early Exploration of Embedded Systems using Portable Test and Stimulus Standard 使用便携式测试和激励标准的嵌入式系统早期探索方法

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893231

Frederik Kautz, Holger Blume, C. Sauer

{"title":"Methodology for an Early Exploration of Embedded Systems using Portable Test and Stimulus Standard","authors":"Frederik Kautz, Holger Blume, C. Sauer","doi":"10.1109/SBCCI55532.2022.9893231","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893231","url":null,"abstract":"The complexity of modern embedded systems, especially in the areas of health, Internet of Things (IoT), or Cyber Physical Systems is continuously increasing. Due to simultaneously decreasing time to market, methods and techniques for a disciplined early Design Space Exploration (DSE) become mandatory. Recently, the Portable Test and Stimulus Standard (PSS) was introduced as a more abstract level to describe test intend, helping with software driven verification of complex systems. Our work aims at its use early in the design cycle, which still suffers from non-optimal representation of applications namely regarding expressiveness, early availability, reuse and path to implementation. Following an analysis of recent work, we propose an early DSE methodology based on PSS following the Y-chart to tackle before mentioned aspects. From a UML like description of a high-end hearing aid algorithm, we show the first needed steps to create valid application-to-architecture mappings, which can be used for further trade-off analysis and reused within and between common development cycles.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127580950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Circuit Reliability Analysis with Considerations of Aging Effect 考虑老化效应的电路可靠性分析

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893233

Suoyue Zhan, Chunhong Chen

引用次数: 0

High-Level Design of a 14-bit Continuous-Time Sigma-Delta Modulator with FIR DAC for Low-Voltage Audio Devices 用于低压音频器件的带FIR DAC的14位连续σ - δ调制器的高级设计

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893239

Matheus Cortez, A. Girardi, P. Aguirre

{"title":"High-Level Design of a 14-bit Continuous-Time Sigma-Delta Modulator with FIR DAC for Low-Voltage Audio Devices","authors":"Matheus Cortez, A. Girardi, P. Aguirre","doi":"10.1109/SBCCI55532.2022.9893239","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893239","url":null,"abstract":"Currently, mobile and wearable devices have digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level design of a continuous-time third-order sigma-delta modulator with a FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. It was estimated that the first-integrator amplifier needs a gain of 50 dB, a GBW of 5 MHz and a slew-rate of at least $3 mathrm{V}/mu mathrm{s}$. By implementing this amplifier in VerilogA and performing a transient simulation with noise, the modulator obtained an SNR of 86.63 dB, an SNDR of 86.46 dB and an ENOB of 14.07 bits. Finally, the extraction of the initial parameters for the amplifier design proved to be satisfactory, since the modulator performance results were within the specified in the design.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130772972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Design Procedure for Sizing Comparators in Active Rectifiers using $g_{m}/I_{D}$ Technique 采用$g_{m}/ $ I_{D}$技术设计有源整流器中比较器的尺寸

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893249

A. Ballo, A. D. Grasso, M. Privitera

引用次数: 0

Hardware Design for the Separable Symmetric Normalized Wiener Filter of the AV1 Decoder AV1解码器可分离对称归一化维纳滤波器的硬件设计

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893219

Roberta Palau, Wagner Penny, J. Goebel, Eduardo Zummach, G. Corrêa, M. Porto, L. Agostini

引用次数: 1

Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design 增强异步电路设计流程以支持复杂的数字系统设计

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893258

M. Sartori, W. Nunes, Ney Laert Vilar Calazans

{"title":"Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design","authors":"M. Sartori, W. Nunes, Ney Laert Vilar Calazans","doi":"10.1109/SBCCI55532.2022.9893258","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893258","url":null,"abstract":"Robustness to variations is desirable in current digital circuit design techniques. Sources of variations are many, and the evolution of current integrated circuit fabrication technologies does increase the amount of such sources and the complexity of ensuring circuit robustness against them. Some design paradigms naturally counter variations to one or more variation sources. Asynchronous quasi-delay insensitive design is such a paradigm, providing robustness to process, supply voltage, temperature, ageing and IR drop variations. This paper proposes an enhancement to Pulsar, a recently proposed open source automated flow for the design of quasi-delay insensitive circuits. A new set of abstract components enables the description of choices and decisions about the flow of data tokens inside asynchronous circuits. These components are now available to be used in the design capture phase of Pulsar. To build circuit cells that implement the abstract (synthesis-enabled) components, this paper brings the proposal of the handshaking mutex (HM), a versatile complex gate that eases the design of asynchronous arbiters. Results demonstrate the new flow is more powerful than the baseline version, enabling the automated synthesis of complex asynchronous circuits.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123083530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Study of Motion Coding Schemes for Learned Video Compression 基于学习视频压缩的运动编码方案研究

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893226

Peng Chen, C. Lin, Wen-Hsiao Peng

{"title":"A Study of Motion Coding Schemes for Learned Video Compression","authors":"Peng Chen, C. Lin, Wen-Hsiao Peng","doi":"10.1109/SBCCI55532.2022.9893226","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893226","url":null,"abstract":"This paper presents a study of motion coding schemes for learned video compression. Most learned video compression systems explicitly signal optical flow maps to characterize motion between video frames for motion compensation. The flow maps, usually of the same size as the video frames, represent a considerable portion of the compressed bitstream. This work studies several schemes to make a non-linear prediction of the flow maps for efficient motion coding. These include signaling an incremental flow map between a coding frame and a motion-compensated frame derived from the flow map predictor. In forming the flow map predictor, we propose a learned motion extrapolation module and a motion forward warping scheme. They are further incorporated into two novel approaches, termed double warping and frame synthesis with motion forward warping, in creating an inter-frame predictor by combining the incremental flow and the flow map predictor. Extensive experiments are conducted to analyze the merits and faults of these variants, and demonstrate their superiority to predictive motion coding and intra motion coding.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116733097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0