Circuit Reliability Analysis with Considerations of Aging Effect

Abstract

Aging effect is one of the critical factors causing circuit reliability degradation due to negative bias temperature instability (NBTI) with continuous and intense logic operation. While there is no lack of research work on aging-related reliability analysis at transistor- or gate-level, little has been done to estimate the reliability at circuit-level. This makes it difficult for the designers to predict the circuit lifetime. To fill this gap, this paper proposes a reliability estimation model to target the reliability degradation at the output of integrated circuits. Simulations on benchmark circuits show that the reliability degradation rate ranges from 1.5% to 8.2% over one-year period, depending on specific circuits.