A custom interconnection multi-FPGA framework for distributed processing applications

C. Salazar-García, A. Chacón-Rodríguez, R. Rímolo-Donadío, R. García-Ramírez, David Solórzano-Pacheco, Jeferson González-Gómez, C. Strydis
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引用次数: 2

Abstract

The development of multi-FPGA systems focused on high-performance computing requires high-speed channels, low bandwidth overhead and latency. In this paper, we propose a multi-FPGA interconnection framework aimed at distributed processing applications. Our solution allows efficient communication between different processing elements distributed among the FPGAs. To evaluate our proposal, we built a multi-FPGA system composed of five Zynq ZC706 FPGA boards capable of hosting a diverse number of coprocessors distributed over our custom network. With an aggregate bandwidth of up to 25 Gbps per FPGA board, the interconnection framework reaches a latency of only 200.36 ns, one of the lowest reported in the lElectronics Engineering, iterature. Experimental results show a computational efficiency of 97.25 % with a sustained throughput of 21.4 GFLOPS. Furthermore, the proposed network interconnection architecture is easily portable to the latest generation FPGAs. This makes the current proposal a competitive option for distributed processing in multi-FPGA systems.
分布式处理应用的自定义互连多fpga框架
以高性能计算为核心的多fpga系统的发展需要高速通道、低带宽开销和低延迟。在本文中,我们提出了一个针对分布式处理应用的多fpga互连框架。我们的解决方案允许分布在fpga之间的不同处理元件之间的有效通信。为了评估我们的建议,我们构建了一个多FPGA系统,该系统由五块Zynq ZC706 FPGA板组成,能够托管分布在我们自定义网络上的不同数量的协处理器。每个FPGA板的总带宽高达25 Gbps,互连框架的延迟仅为200.36 ns,是电子工程文献中报道的最低延迟之一。实验结果表明,该算法的计算效率为97.25%,持续吞吐量为21.4 GFLOPS。此外,所提出的网络互连架构易于移植到最新一代的fpga上。这使得当前的方案成为多fpga系统中分布式处理的一个有竞争力的选择。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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