2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第3页

A Time-Efficient Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits 模拟与混合信号(AMS)电路的缺陷仿真框架

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893224

M. Saikiran, Mona Ganji, Degang Chen

{"title":"A Time-Efficient Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits","authors":"M. Saikiran, Mona Ganji, Degang Chen","doi":"10.1109/SBCCI55532.2022.9893224","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893224","url":null,"abstract":"Defect simulation time in AMS circuits is rapidly growing due to increasing circuit complexity, especially in safety-critical automotive applications which needs to meet very high defect coverage (usually >90%). Reduction in defect simulation time directly translates into reduction in overall development time. In this work, we propose a time-efficient framework to simulate various defects during pre-silicon testing of AMS circuits. The proposed method uses Verilog-A modules to realize a given defect model and tests nearly all the defects in a circuit with a single test run (for a given test condition) depending on the defect-detection scheme. To strongly validate our framework, we use two distinct defect detection schemes for operational amplifiers. The first detection scheme is the intentional offset injection (IOI) method which, predominantly, is a DC testing scheme. For this scheme, the proposed framework achieved a time-saving factor of more than 10X compared to the conventional framework. The second scheme is the oscillation test method (OTM) which is a transient testing scheme. For this OTM scheme, we show that the proposed framework can reduce the simulation time to less than 50% of the conventional simulation time. We also show that the proposed framework has no negative impact on defect coverage.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116221222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Energy-Efficient Forwarding Routing Algorithm with bidirectional link quality estimator for Wireless Sensor Networks 基于双向链路质量估计的无线传感器网络节能转发路由算法

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893221

Hugo Rodríguez, Jimmy Tarrillo

引用次数: 0

Deep Neural Network Feasibility Using Analog Spiking Neurons 使用模拟尖峰神经元的深度神经网络可行性

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893216

Thomas Soupizet, Zalfa Jouni, João F. Sulzbach, A. Benlarbi-Delai, Pietro M. Ferreira

引用次数: 3

35th SBCCI 2022 Proceedings 第35届SBCCI 2022会议录

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/sbcci55532.2022.9893225

引用次数: 0

PANACA: An Open-Source Configurable Network-on-Chip Simulation Platform PANACA:一个开源可配置的片上网络仿真平台

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893260

Julian Haase, Alexander Groß, Maximilian Feichter, D. Göhringer

引用次数: 1

Thermal-Aware Thread and Turbo Frequency Throttling Optimization for Parallel Applications 并行应用的热感知线程和涡轮频率节流优化

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893245

Sandro M. Marques, F. Rossi, M. C. Luizelli, A. C. S. Beck, A. Lorenzon

{"title":"Thermal-Aware Thread and Turbo Frequency Throttling Optimization for Parallel Applications","authors":"Sandro M. Marques, F. Rossi, M. C. Luizelli, A. C. S. Beck, A. Lorenzon","doi":"10.1109/SBCCI55532.2022.9893245","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893245","url":null,"abstract":"The number of processing cores in multicore pro-cessors has been rising to deal with the levels performance required by modern applications. Concomitantly, the operating temperature of hardware components has become a primary concern due to economic and environmental perspectives. Hence, different software (e.g., thread throttling) and hardware (e.g., dynamic voltage and frequency scaling - DVFS) strategies have also been applied to reduce the processor temperature levels without jeopardizing the application's performance. While thread throttling strategies artificially tune the degree of thread-level parallelism of applications to improve the hardware resources utilization according to their scalability issues, turbo frequencies have been employed to speed up the execution of a given appli-cation by increasing the processor's frequencies above the base. Given that, we propose Urano. It is a thermal-aware strategy that combines thread throttling and turbo mode optimization to diminish the processor operating temperature without penalizing the performance of the application. Through the execution of twelve well-known parallel applications on a modern multicore architecture, we demonstrate that Urano decreases the peak temperature by up to 17% compared to how parallel applications are executed with minimal impact on the performance.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"55 51","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120888939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Throughput Multifilter VLSI Design for the AV1 Fractional Motion Estimation AV1分数阶运动估计的高通量多滤波器VLSI设计

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893255

Daiane Freitas, Bruna Nagai, M. Grellert, C. Diniz, G. Corrêa

{"title":"High-Throughput Multifilter VLSI Design for the AV1 Fractional Motion Estimation","authors":"Daiane Freitas, Bruna Nagai, M. Grellert, C. Diniz, G. Corrêa","doi":"10.1109/SBCCI55532.2022.9893255","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893255","url":null,"abstract":"A main challenge for emerging video encoders is the high complexity introduced by their new encoding tools. In the royalty-free AV1 (AOMedia Video 1) codec, a large part of this complexity is focused on the inter prediction stage. This is particularly given to fractional motion estimation (FME), where a large number of FIR (Finite Impulse Response) type filters is used in the process of interpolation that generates fractional position samples given the integer position samples as input. Therefore, strategies to mitigate this complexity, such as designing hardware accelerators, are needed. Another recurring concern is the power dissipated as many users consume video media using battery-constrained devices. Based on that, this work introduces a dedicated multifilter hardware architecture for the AV1 codec interpolation filters with a focus on the motion estimation stage. The proposal implements the Regular, Sharp and Smooth filter families, using the operand isolation technique to avoid unnecessary power consumption. The designed architecture is capable of achieving a processing throughput of 3187.5 Msamples/sec for ME (Motion Estimation) operation, and can interpolate 8k videos resolution at 60 frames per second considering the MC (Motion Compensation) scenario.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129607585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Exploring Machine Learning for Electrical Behavior Prediction: The CMOS Inverter Case Study 探索机器学习的电行为预测:CMOS逆变器案例研究

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893261

Gabriel Lima Jacinto, L. Y. Imamura, M. Grellert, C. Meinhardt

{"title":"Exploring Machine Learning for Electrical Behavior Prediction: The CMOS Inverter Case Study","authors":"Gabriel Lima Jacinto, L. Y. Imamura, M. Grellert, C. Meinhardt","doi":"10.1109/SBCCI55532.2022.9893261","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893261","url":null,"abstract":"With the advancement of integrated circuit man-ufacturing technology, a growing number of aspects must be considered during the electrical characterization of circuits in order to solve challenges such as the effect of process variability. This increases the characterization time due to the use of techniques based on exhaustive electrical simulations. Machine learning techniques are consistently being employed to assist digital design at many levels of abstraction with various successful applications. Thus, the main objective of this work is to evaluate machine learning regression algorithms as an alternative to ex-haustive electrical simulation in the cell characterization project. In this step, multiple linear regression, support vector regression, decision trees, and random forest algorithms are considered. This work presents the results of a first case study: an Inverter using bulk CMOS technology. Specifically, the energy values and propagation times of this circuit will be separately predicted. A comparative analysis is done for each dependent variable between the models in order to understand which is the best regression model for the task. The algorithm with the lowest cost function proved to be Random Forests, with a R2 above 98% for all predicted variables.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130046465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Frequency Non-Separable Transform Hardware System Design for the VVC Encoder VVC编码器的低频不可分变换硬件系统设计

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893228

J. Goebel, L. Agostini, B. Zatt, M. Porto

引用次数: 1

CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining CSIP:一个紧凑的Scrypt IP设计，具有单个PBKDF2核心，用于区块链挖掘

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893217

V. Le, Pham Hoai Luan, T. Tran, Y. Nakashima

{"title":"CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining","authors":"V. Le, Pham Hoai Luan, T. Tran, Y. Nakashima","doi":"10.1109/SBCCI55532.2022.9893217","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893217","url":null,"abstract":"Developing compact and energy-efficient Scrypt hardware for power-constrained devices is necessary to balance the distribution of blockchain networks. However, existing Scrypt circuits are challenging to achieve in a compact area and energy-efficient since they focus only on maximizing hash performance. Therefore, this paper proposes a Compact Scrypt IP (CSIP) architecture to reduce power consumption while maintaining hashing performance for blockchain mining. Specifically, CSIP uses only one SHA-256 core inside one PBKDF2 core to minimize hardware resources, thus decreasing power consumption significantly. Furthermore, CSIP supports the configuration of parameters to suit the various requirements of blockchain mining. The CSIP design is successfully implemented and verified on a Xilinx Zynq UltraScale+ MPSoC ZCU102 FPGA at a system-on-chip level. Accordingly, the energy efficiency of the CSIP on ZCU102 FPGA is 322 times and 9 times higher than Intel i9-10940X CPU and Nvidia Tesla V100 GPU, respectively. Finally, the experimental results on Xilinx Virtex-7 VC707 FPGA show that the proposed CSIP is significantly better than existing Scrypt architectures in area, power, and energy efficiency.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115328148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2