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2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献

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Design-Time Analysis of Real-Time Traffic for Networks-on-Chip using Constraint Models 基于约束模型的片上网络实时流量设计时分析
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893222
Anderson R. P. Domingues, S. J. Filho, A. M. Amory, F. Moraes
{"title":"Design-Time Analysis of Real-Time Traffic for Networks-on-Chip using Constraint Models","authors":"Anderson R. P. Domingues, S. J. Filho, A. M. Amory, F. Moraes","doi":"10.1109/SBCCI55532.2022.9893222","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893222","url":null,"abstract":"Real-time networks-on-chips (RT-NoCs) were proposed to suit the needs of communication-intensive systems with real-time requirements. However, most of the current implementations found in the literature are based on custom routers, thus requiring a complete redesign of the interconnect architecture. This work presents a novel approach to tackle the analysis and scheduling of real-time traffic that requires no special mechanism to be implemented within the NoC design. Our solution relies on an auxiliary hardware module to synchronize the injection of packets into the network instead of custom routers, benefiting existing non-RT NoC designs. Our approach guarantees scheduled traffic to be congestion-free by using a design-time optimization process. Results present a didactic proof-of-concept using a synthetic application mapped onto a small NoC design.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124827724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Protecting SRAM PUF from BTI Aging-based Cloning Attack 保护SRAM PUF免受基于BTI老化的克隆攻击
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893248
Shengyu Duan, G. Sai
{"title":"Protecting SRAM PUF from BTI Aging-based Cloning Attack","authors":"Shengyu Duan, G. Sai","doi":"10.1109/SBCCI55532.2022.9893248","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893248","url":null,"abstract":"SRAM Physical Unclonable Function (PUF) is currently one of the most popular PUFs, practically adopted in IC productions, to perform security primitives like encryption. However, previous works suggest responses of an SRAM PUF may be changeable due to one of the CMOS aging effects, Bias Temperature Instability (BTI). A physical counterfeit is thereby able to be produced by using BTI to change its responses, based on those of a target PUF. To prevent the BTI-based physical cloning attack, we propose a scheme without any modifications on the current SRAM PUF circuit, which is to pre-charge a challenged cell before it is powered up, so that its response can be affected by those transistors that cannot be precisely aged in the cloning process. We also show security and reliability metrics of SRAM PUFs are not affected by the extra pre-charge phase.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126120018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low Noise Broadband Amplifier for Breast Cancer System 用于乳腺癌系统的低噪声宽带放大器
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893241
Leonardo Rodrigues Leopoldo, W. Noije
{"title":"Low Noise Broadband Amplifier for Breast Cancer System","authors":"Leonardo Rodrigues Leopoldo, W. Noije","doi":"10.1109/SBCCI55532.2022.9893241","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893241","url":null,"abstract":"This work proposes to develop a Low Noise Broadband Amplifier in CMOS 180nm tecnology, with supply voltage of 1.8V. The circuit has three stages, the first a common gate amplifier, followed by a common source amplifier, finally a buffer to assist in the measurement. It achieves a noise figure slightly higher than 6.3dB, an area of 0.17mm2 without the pad-ring, consumption of 7.3mW, a band above 10dB from 2.5GHz to 8.1GHz, the gain varies between 10 to 16.9dB, and port isolation is less than -10dB for the entire range. The block is an integral part of a breast cancer system receiver, but finds other applications in IoT and healthcare industries.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124118496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High-level Model to Leverage NoC-based Many-core Research 利用基于noc的多核研究的高级模型
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893235
I. I. Weber, Angelo Elias Dalzotto, F. Moraes
{"title":"A High-level Model to Leverage NoC-based Many-core Research","authors":"I. I. Weber, Angelo Elias Dalzotto, F. Moraes","doi":"10.1109/SBCCI55532.2022.9893235","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893235","url":null,"abstract":"This work presents Chronos-V, a Many-Core System-on-Chip (MCSoC) that adopts abstract hardware mod-eling, executing the freeRTOS Operating System (OS) at each processing element (PE). The system architecture contains two regions: (i) General Purpose Processing Elements (GPPE), re-sponsible for executing user applications; (ii) peripherals that provide IO capabilities or hardware acceleration to the system. The freeRTOS kernel provides scheduling for application tasks, with modules added to it providing a Message Passing Interface (MPI) and system management. The goal is to provide a platform with a parameterizable hardware model that allows software development and evaluation of system management techniques. Results evaluate the simulation speedup by comparing the ab-stract model simulation against an RTL simulation in systems with up to 100 PEs, and thermal management techniques added to the freeRTOS as an API.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115800553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.3 to 5-MHz Low-Voltage Digitally-Controlled Oscillator for Energy Harvesting Applications 用于能量收集应用的0.3至5 mhz低压数字控制振荡器
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893232
L. F. M. Dutra, A. Girardi, L. Severo
{"title":"A 0.3 to 5-MHz Low-Voltage Digitally-Controlled Oscillator for Energy Harvesting Applications","authors":"L. F. M. Dutra, A. Girardi, L. Severo","doi":"10.1109/SBCCI55532.2022.9893232","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893232","url":null,"abstract":"Energy Harvesting is the act of collecting energy from the environment and transforming it into electrical energy. Energy Harvesters in integrated-form are composed of many components, including a DC-DC converter. If this converter is implemented with switched-capacitors, an oscillator is necessary to provide the switching frequency. There is a great demand for ultra-low power and ultra-low voltage oscillators in Energy Harvesting applications, since switching frequency of the DC-DC converter can be adjusted to optimize conversion efficiency. This work proposes a 0.7 V open-loop digitally-controlled oscillator (DCO) in a frequency range of 300 kHz to 5 MHz and maximum power consumption of $5 mu mathrm{W}$ in the TSMC 180 nm technology. It is based on a ring-oscillator with variable capacitive loading for a fine adjustment in frequency and current-starving transistors for frequency calibration. The frequency setting is performed with a 4-bit digital input. The implemented circuit layout occupies an area of 0.0348 mm2. Post-layout simulations have shown monotonic and linear frequency variation with a peak power consumption of $4.9 mu mathrm{W}$ at the maximum frequency of 5 MHz. The calibration capability compensates frequency degradation in post-layout simulations due to significant parasitic capacitances.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127754745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An UHD 4K@60fps Dual Self-Guided Filter Targeting the AV1 Decoder 针对AV1解码器的超高清4K@60fps双自导滤波器
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893236
Roberta Palau, J. Goebel, Eduardo Zummach, Ramiro Viana, M. Corrêa, G. Corrêa, M. Porto, L. Agostini
{"title":"An UHD 4K@60fps Dual Self-Guided Filter Targeting the AV1 Decoder","authors":"Roberta Palau, J. Goebel, Eduardo Zummach, Ramiro Viana, M. Corrêa, G. Corrêa, M. Porto, L. Agostini","doi":"10.1109/SBCCI55532.2022.9893236","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893236","url":null,"abstract":"This paper presents the first dedicated hardware design in the literature for the Dual Self-Guided Filter (DSGF) from the AOM Video 1 (AV1) video format. The DSGF is one of the last filters in the encoding loop and is used to attenuate blurring artifacts and to improve the subjective video quality. The presented hardware design targets the AV1 decoder and it is able to process Ultra-High Definition (UHD) videos with $3840times 2160$ pixels per frame at 60 frames per second when running at 212.86 MHz. The architecture was synthesized to standard cells using the 40 nm TSMC library, using 177.58 kgates and with a power dissipation of 120.21mW.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127812436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Advanced Thermal Management using Approximate Computing and On-Chip Thermoelectric Cooling 先进的热管理使用近似计算和片上热电冷却
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893242
Hammam Kattan, H. Amrouch
{"title":"Advanced Thermal Management using Approximate Computing and On-Chip Thermoelectric Cooling","authors":"Hammam Kattan, H. Amrouch","doi":"10.1109/SBCCI55532.2022.9893242","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893242","url":null,"abstract":"In this work, we investigate the effectiveness of approximate computing and on-chip thermoelectric cooling on mitigating and managing the on-chip temperatures. On the first hand, approximate computing has emerged in the last decade as an attractive computing paradigm that offers a powerful trade-off between power and accuracy. For deep learning ap-plications, approximations in computing may not always lead to an observable loss in accuracy. This largely depends on the sensitivity of the executed DNN models. On the other hand, on-chip cooling using novel ultra thin-film Thermoelectric (TE) devices has also emerged as an attractive powerful means for heat dissipation to suppress excessive on-chip power densities. Our investigations are done using commercial ANSYS tool flows that employ accurate Finite Elements Analysis (FEA). This enables us to accurately study the Peltier's effect (for cooling purposes) as well as the Seebeck's effect (for energy harvesting purposes) demonstrating the promise and effectiveness of on-chip cooling using Thermoelectric devices.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129937842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transistor Reordering for Electrical Improvement in CMOS Complex Gates CMOS复合栅极电性改进的晶体管重新排序
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893256
Marcello M. Muñoz, Henrique Kessler, Marcelo Porto, V. Camargo
{"title":"Transistor Reordering for Electrical Improvement in CMOS Complex Gates","authors":"Marcello M. Muñoz, Henrique Kessler, Marcelo Porto, V. Camargo","doi":"10.1109/SBCCI55532.2022.9893256","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893256","url":null,"abstract":"As the automated design of supergates becomes possible, techniques to improve their electrical characteristics grow in relevance. Among the design choices, the order of transistors affects the delay and power dissipation. This paper presents an adaptation of an established transistor reordering algorithm targeting electric gains. The proposed algorithm re-orders using both the probability of the transistor being active and the nature of the transistor's input. Electrical simulations were run for the 4 input P-Class functions, and the proposed algorithm obtains gains in the average power, static power, average delay, and critical delay. Among the logic gates with different designs from the baseline algorithm, the proposed algorithm produced logic gates with smaller power and critical delay in 2146 (63.36%) and 478 (69.38%) of the functions using two design strategies. This paper presents that the transistors' input delay must be considered when reordering transistors for electrical improvement in supergates.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114395572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC 为时间辅助SAR ADC设计9.3μW低功耗时数转换器(TDC)
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893250
Rodrigo N. Wuerdig, Bruno Canal, T. Balen, S. Bampi
{"title":"Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC","authors":"Rodrigo N. Wuerdig, Bruno Canal, T. Balen, S. Bampi","doi":"10.1109/SBCCI55532.2022.9893250","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893250","url":null,"abstract":"The Time-to-Digital Converter (TDC) is an impor-tant circuit block for digitally quantifying the time displacement between digital events. Among several applications of the TDC, this work focuses on its application to low-power Successive-approximation Analog-to-Digital Converters (SAR ADC). The TDC can assist the SAR algorithm to improve the energy efficiency of capacitive DAC switching schemes, which constitute a significant portion of the SAR ADC power dissipation. This work presents the design of a coarse 8-bit deep TDC in a manufacturable 28 nm Bulk CMOS technology, which displays good coverage of the SAR ADC input after a calibration step using tunable delay cells that were optimized for 0.6 V supply. In our design approach, we optimized for energy the sizing of the both delay cells and the LV registers. The TDC had a simulated mean power dissipation of just $9.25 mu W$ at this voltage, making it a good candidate for applications that are not very demanding in terms of precision.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133857482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing 利用去耦单元和晶体管尺寸提高全加法器电路的软误差鲁棒性
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2022-08-22 DOI: 10.1109/SBCCI55532.2022.9893240
Rafael N. M. Oliveira, F. A. D. Silva, Ricardo Reis, R. Schvittz, C. Meinhardt
{"title":"Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing","authors":"Rafael N. M. Oliveira, F. A. D. Silva, Ricardo Reis, R. Schvittz, C. Meinhardt","doi":"10.1109/SBCCI55532.2022.9893240","DOIUrl":"https://doi.org/10.1109/SBCCI55532.2022.9893240","url":null,"abstract":"This paper evaluates the radiation sensitivity of the Mirror and Hybrid Full Adders topologies at nominal and near-threshold voltage. The circuits are designed and electrical simulated adopting the 7 nm ASAP FinFET technology. Also, two mitigation approaches are considered on these circuits: Decoupling Cell and Transistor Sizing individually and combined. Considering soft errors, exploring Transistor Sizing increases $boldsymbol{3}mathrm{x}$ to $boldsymbol{4}mathrm{x}$ the robustness of the Mirror FA, for nominal and near-threshold operation, respectively. Both techniques reduces the total error occurrence over 35% for the investigated FAs circuits.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131543030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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