Miniaturized Sign-Magnitude Stochastic-Binary FIR Filter Architecture with Enhanced Accuracy

Abstract

This paper presents a stochastic-binary hybrid ar-chitecture for miniaturizing FIR filters and its comparison with established filter implementations. FPGA realization of 4-, 16-and 64-tap FIR filters with 8-bit word length has confirmed the worthiness of the proposed architecture in densely packed systems. FPGA resources reduces by $\sim 53\%$ in a 4 - tap FIR filter, with the architecture's area efficiency increasing with filter taps. This hybrid architecture, performing multiplication in stochastic and accumulation in binary domain, requires only 2 random number generators, one for tapped delay-line and the other for filter coefficients. Thanks to additive-recurrence-based low-discrepancy sequences in stochastic number generators and non-scaled binary accumulation, the proposed stochastic architecture achieves best-in-class performance. This is validated via a detailed analysis of a 16-tap filter that achieves a pass-band ripple of $A_{p}=0.58dB$ and a stop-band attenuation of $A_{st}=-31.46dB$, making it indistinguishable from binary implementations. Additionally, a mathematical approach is pre-sented to estimate the error in the filter output, well before its actual realization. ASIC synthesis of a 16-tap FIR filter based on the proposed architecture with area of only 30,165 $\mu m^{2}$ is superior to all discussed filter structures: It grants 68% area reduction compared to its binary counterpart and consumes an energy per operation of 0.429 nJ, a value at least $1.8\times$ lower than previous stochastic designs.