{"title":"面向区块链物联网应用的灵活节能BLAKE-256/2s协处理器","authors":"Pham Hoai Luan, T. Tran, V. Le, Y. Nakashima","doi":"10.1109/SBCCI55532.2022.9893257","DOIUrl":null,"url":null,"abstract":"Developing flexible and energy-efficient BLAKE-256/2s hardware has recently become necessary since BLAKE-256 and BLAKE2s are important cryptographic hash functions in reliability and security enhancement for blockchain-based IoT applications. However, previous BLAKE-256/2s architectures are challenging in achieving high flexibility and energy efficiency. Therefore, this paper proposes the BLAKE-256/2s co-processor to achieve high flexibility and energy efficiency for blockchain-based IoT applications. The proposed BLAKE-256/2s accelerator has three novel optimization techniques to achieve those goals. First, a configurable hashing core is proposed to enhance flexibility. Second, a pipelined permutation and compression architecture are developed to improve the throughput and hardware efficiency. Third, a mining transmission mechanism is introduced to optimize the performance of our co-processor at the system-on-chip level. The proposed co-processor is implemented and verified on a Xilinx Zynq $\\mathbf{UltraScale}+$ MPSoC ZCU102 FPGA. Accordingly, the power and energy efficiency of the co-processor on the ZCU102 FPGA is significantly better than the Intel i9 10940X CPU and the RTX 3090 GPU. Moreover, experimental results on several FPGAs prove that the proposed co-processor is considerably higher throughput, area efficiency, and flexibility than FPGA-based related works.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications\",\"authors\":\"Pham Hoai Luan, T. Tran, V. Le, Y. Nakashima\",\"doi\":\"10.1109/SBCCI55532.2022.9893257\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Developing flexible and energy-efficient BLAKE-256/2s hardware has recently become necessary since BLAKE-256 and BLAKE2s are important cryptographic hash functions in reliability and security enhancement for blockchain-based IoT applications. However, previous BLAKE-256/2s architectures are challenging in achieving high flexibility and energy efficiency. Therefore, this paper proposes the BLAKE-256/2s co-processor to achieve high flexibility and energy efficiency for blockchain-based IoT applications. The proposed BLAKE-256/2s accelerator has three novel optimization techniques to achieve those goals. First, a configurable hashing core is proposed to enhance flexibility. Second, a pipelined permutation and compression architecture are developed to improve the throughput and hardware efficiency. Third, a mining transmission mechanism is introduced to optimize the performance of our co-processor at the system-on-chip level. The proposed co-processor is implemented and verified on a Xilinx Zynq $\\\\mathbf{UltraScale}+$ MPSoC ZCU102 FPGA. Accordingly, the power and energy efficiency of the co-processor on the ZCU102 FPGA is significantly better than the Intel i9 10940X CPU and the RTX 3090 GPU. Moreover, experimental results on several FPGAs prove that the proposed co-processor is considerably higher throughput, area efficiency, and flexibility than FPGA-based related works.\",\"PeriodicalId\":231587,\"journal\":{\"name\":\"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)\",\"volume\":\"80 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-08-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SBCCI55532.2022.9893257\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBCCI55532.2022.9893257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications
Developing flexible and energy-efficient BLAKE-256/2s hardware has recently become necessary since BLAKE-256 and BLAKE2s are important cryptographic hash functions in reliability and security enhancement for blockchain-based IoT applications. However, previous BLAKE-256/2s architectures are challenging in achieving high flexibility and energy efficiency. Therefore, this paper proposes the BLAKE-256/2s co-processor to achieve high flexibility and energy efficiency for blockchain-based IoT applications. The proposed BLAKE-256/2s accelerator has three novel optimization techniques to achieve those goals. First, a configurable hashing core is proposed to enhance flexibility. Second, a pipelined permutation and compression architecture are developed to improve the throughput and hardware efficiency. Third, a mining transmission mechanism is introduced to optimize the performance of our co-processor at the system-on-chip level. The proposed co-processor is implemented and verified on a Xilinx Zynq $\mathbf{UltraScale}+$ MPSoC ZCU102 FPGA. Accordingly, the power and energy efficiency of the co-processor on the ZCU102 FPGA is significantly better than the Intel i9 10940X CPU and the RTX 3090 GPU. Moreover, experimental results on several FPGAs prove that the proposed co-processor is considerably higher throughput, area efficiency, and flexibility than FPGA-based related works.