{"title":"Object-oriented video coding algorithm for very low bit-rate system","authors":"Liang-Gee Chen, You-Ming Chiu, T. Chiueh, H. Jong","doi":"10.1109/APCCAS.1994.514622","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514622","url":null,"abstract":"In this paper, a video coding method based on region segmentation is proposed. It is designed for very low bit-rate systems such as video-phone and video-conferencing. Instead of block-based coding, we adopt an object-oriented approach, which first calculates the motion vector of each pixel using a modified optical flow approach, then segments the motion field into circumscribed rectangular regions that can be efficiently coded. Simulation results of several typical image sequences reveal that the proposed algorithm is both effective and of high performance.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125734834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new concept of a Gm tuning circuit for voltage- or current-controlled transconductance circuits","authors":"A. Hyogo, K. Sekine","doi":"10.1109/APCCAS.1994.514616","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514616","url":null,"abstract":"A new concept of a transconductance (Gm) tuning circuit using switched-capacitor (SC) circuits for voltage- or current-controlled transconductance circuits is proposed. This concept uses an integrator which is controlled by time (or frequency) as a current-to-voltage converter for tuning. The Gm can be determined by the integrated time of the current from the transconductance circuit, the integration capacitor and the reference voltage(s). Moreover, the Gm control voltage produced by the proposed circuit has no ripple. The proposed circuit can tune operational transconductance amplifiers, MOS resistive circuits and so on. Finally, an offset voltage cancellation technique for the integrator is shown. SPICE simulations are performed to verify the performance of the proposed circuits.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126517117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast inverters and dividers for finite field GF(2/sup m/)","authors":"Y. Horng, Shyue-Win Wei","doi":"10.1109/APCCAS.1994.514550","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514550","url":null,"abstract":"Based on Euclid's algorithm, two architectures for performing rapid inversions and divisions in finite field GF(2/sup m/) with the standard basis representation are presented. Both architectures have regularity and modularity and are well suited for VLSI implementation. These circuits can be easily expanded to any finite field size because they are independent of the primitive polynomial used to generate the field. The proposed inverter and divider take exactly 2(m-1) clock cycles for each inversion and division operation, and the clock period is independent of the field size m.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127739028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optical fiber digital picture code and supervisory signal transmission system","authors":"H. Asada, H. Ikeda, H. Yoshida","doi":"10.1109/APCCAS.1994.514575","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514575","url":null,"abstract":"This paper describes a digital signal transmission system using nine optical fibers for the picture code of 5 bits and supervisory signal of 3 bits, and using one optical fiber for the clock at 14.32 MHz, which is built based on the conventional digital TV signal transmission system consisting of a picture code of 8 bits with the clock at 14.32 MHz. Since the picture code and supervisory signals are transmitted at the same time, the system can be used for industrial applications in an inferior environment. Even if the environment is dangerous for human beings, the system can be operated satisfactorily. The experimental system succeeded in transmitting the TV signal, and the picture quality was almost the same as that operating at 8 quantizational bits. Since the TV and supervisory signals are digitized in the same sequence, these signals are suitable for computer processing.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134190125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Channel noise filtering for subband image coding using vector quantization","authors":"C. Kuo, J. H. Leu","doi":"10.1109/APCCAS.1994.514625","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514625","url":null,"abstract":"In this paper, we design a post-filter for the subband coding of images using vector quantization. The purpose of this filter is to remove the inevitable channel noise after the compressed image is transmitted across a channel. We first proposed two simple schemes to detect the edges and channel noises in the subbands based on the image and subband characteristics. Then the noise corrupted subbands at the uniform, edge, and texture region are then adaptively low-pass filtered. After noise filtering, the image is then reconstructed from all its subbands. Since the proposed filter does not assume any knowledge about the quantization, it can be used for any subband coding schemes. The experimental results show that the proposed filter always improves the coding performance when the channel bit error rate is greater than 0.01%. The largest gain (5.7 dB) occurs when the bit error rate is 1%.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129829284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"BTC image coding with visual patterns","authors":"Tuk Po Chun, B. Zeng, M. L. Liou","doi":"10.1109/APCCAS.1994.514628","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514628","url":null,"abstract":"This paper presents a block truncation coding (BTC) scheme for image compression that employs visual patterns designed independently of the image to be coded. In this method, image blocks are first classified into three classes: uniform, gentle edge, and sharp edge, according to their variations. Design focus is on edge blocks, where two sets of patterns, namely, visual patterns and visual row patterns are used. Different quantization is performed on the mean values of each block according to its block type. Experimental results show that the proposed BTC scheme can achieve PSNR about 30 dB at bit rate 0.46/spl sim/0.53 bpp (for the image Lenna of size 512/spl times/512).","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122196546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling, simulation and layout synthesis for giga scale CMOS VLSI","authors":"S. Kang","doi":"10.1109/APCCAS.1994.514591","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514591","url":null,"abstract":"Summary form only given, as follows. With continuing proliferation of CMOS technology, we are approaching the era of giga-scale VLSI integration with lower power requirement. It would not be surprising to any member of the VLSI community that the validity of many CAD models become obsolete in the deep submicron technology. Also, the required chip complexity increases faster than what designers can afford in even shorter design cycle time. In order to manage the design complexity and contain the increase in the design effort of VLSI chips, it is critically important to fully automate the layout of VLSI circuits in a manner the finished layout meets all the design objectives such as timing, area, reliability constraints with high yield. Here the author considers new MOS models for deep submicron technologies, fast and accurate simulation techniques for VLSI circuits, MOS reliability modeling and diagnosis, and timing-driven layout CMOS synthesis techniques. FPGA, standard cells based design and full custom design cases are considered. For FPGA, timing-driven partitioning is considered along with new CAD tool development trends. For standard cells based design, gate sizing techniques for meeting timing and low-power constraints with minimum area are discussed. For full custom design, an integrated environment for compact layout platforms, triple metal routing techniques and transistor sizing algorithms is discussed.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123697295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of inverse DCT unit and motion compensator for MPEG2 HDTV decoding","authors":"T. Onoye, Y. Morimoto, T. Masaki, I. Shirakawa","doi":"10.1109/APCCAS.1994.514621","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514621","url":null,"abstract":"An MPEG2 video decoder core is implemented, which consists of an inverse discrete cosine transform (IDCT) unit and a motion compensator. By means of butterfly computation, multi-bit extension of distributed arithmetic, and improvement of critical paths, the IDCT unit achieves a high throughput, and the motion compensator calculates half-pel image dynamically so as to cover several types of picture prediction modes employed by MPEG2. The decoder core occupies 27 mm/sup 2/ in a 0.6-/spl mu/m triple-metal CMOS technology, processes a macroblock (16/spl times/16 pels) within 2.5 /spl mu/s, and therefore is capable of decoding HDTV (1920/spl times/1152 pels) resolution images in real time.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127422567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park
{"title":"A VLSI circuit extractor with a parallel algorithm","authors":"K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park","doi":"10.1109/APCCAS.1994.514567","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514567","url":null,"abstract":"This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125897772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A versatile current-mode biquad using operational amplifiers","authors":"Y. Shiwen, S. Tsuiki, M. Ishida, Y. Fukui","doi":"10.1109/APCCAS.1994.514618","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514618","url":null,"abstract":"A versatile current-mode biquad filter using three operational amplifiers and 9 passive elements is proposed. By the suitable choice of the output branch, lowpass, bandpass, highpass, bandstop and allpass transfer functions are realized simultaneously without changing the circuit configuration and elements. Two circuits, one is for low frequency application and the other for high frequency, are proposed. The center frequency, quality factor and gain constants of the circuit can be tuned independently. Simulated results will show that the circuits work successfully.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129911912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}