Fast inverters and dividers for finite field GF(2/sup m/)

Based on Euclid's algorithm, two architectures for performing rapid inversions and divisions in finite field GF(2/sup m/) with the standard basis representation are presented. Both architectures have regularity and modularity and are well suited for VLSI implementation. These circuits can be easily expanded to any finite field size because they are independent of the primitive polynomial used to generate the field. The proposed inverter and divider take exactly 2(m-1) clock cycles for each inversion and division operation, and the clock period is independent of the field size m.