K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park
{"title":"A VLSI circuit extractor with a parallel algorithm","authors":"K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park","doi":"10.1109/APCCAS.1994.514567","DOIUrl":null,"url":null,"abstract":"This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.1994.514567","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm.