A VLSI circuit extractor with a parallel algorithm

K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park
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Abstract

This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm.
基于并行算法的VLSI电路提取器
本文介绍了一种自动CMOS电路提取的并行算法,该算法将集成电路版图转换为适合电路仿真的电路网表。该算法采用可重构并行机架构,实现了恒定时间复杂度的电路提取性能。通过CMOS逆变器的设计,验证了该算法的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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