基于并行算法的VLSI电路提取器

Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems Pub Date : 1994-12-05 DOI:10.1109/APCCAS.1994.514567

K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park

{"title":"基于并行算法的VLSI电路提取器","authors":"K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park","doi":"10.1109/APCCAS.1994.514567","DOIUrl":null,"url":null,"abstract":"This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A VLSI circuit extractor with a parallel algorithm\",\"authors\":\"K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park\",\"doi\":\"10.1109/APCCAS.1994.514567\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm.\",\"PeriodicalId\":231368,\"journal\":{\"name\":\"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.1994.514567\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.1994.514567","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文介绍了一种自动CMOS电路提取的并行算法，该算法将集成电路版图转换为适合电路仿真的电路网表。该算法采用可重构并行机架构，实现了恒定时间复杂度的电路提取性能。通过CMOS逆变器的设计，验证了该算法的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A VLSI circuit extractor with a parallel algorithm

This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems

自引率

0.00%

发文量